DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s filing on 03/14/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 6, 11-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li et al. (“Li”, US Pub 2023/0035838, from same assignee & Applicant’s submitted IDS).
Regarding independent claim 6, Li teaches (Fig. 1-13; Para 24-45) a totem-pole power factor correction converter, comprising:
three input terminals (VLIN, VL2N, VL3N), a neutral terminal (N), and two output terminals (Vo+, Vo-), wherein the three input terminals are connected to an AC power source (AC input source);
a first switch leg (11), a second switch leg (12) and a third switch leg (13) electrically connected to the three input terminals (VLIN, VL2N, VL3N) respectively and electrically connected with each other in parallel (10: parallel connected phase legs ‘11, 12 & 13’; 1st phase leg 11 includes upper switch Q1 connected in series with lower switch Q2 in midpoint N1 corresponding to input terminal VL1N; 2nd phase leg 12 includes upper switch Q3 connected in series with lower switch Q4 in midpoint N2 corresponding to input terminal VL2N’ and 3rd phase leg 13 includes upper switch Q5 connected in series with lower switch Q6 in midpoint N3 corresponding to input terminal VL3N), wherein each of the first switch leg, the second switch leg and the third switch leg comprises an upper switch (Q1, Q3, Q5) and a lower switch (Q2, Q4, Q6) connected in series and has a midpoint (N1, N2, N3) electrically to a corresponding phase of the AC power source (AC input source) through an inductor (boost inductor L1 connected between input terminal VLIN and midpoint N1 of phase leg 11; boost inductor L2 connected between input terminal VL2N and midpoint N2 or phase leg 2; and boost inductor L2 connected between input terminal VL3N and midpoint N3 of phase leg 3);
a diode leg (diode leg 20 connected in parallel with each respective 1st-3rd phase switch legs 11-13; wherein diode leg 20 includes series connected D1-2 at midpoint N4; and N being neutral terminal connected to midpoint N4 of diode leg 20, when switch RLG=on), electrically connected in parallel to the first switch leg (11), the second switch leg (12), and the third switch leg (13), and comprising two diodes connected in series (D1-2 connected in series at a midpoint N4), wherein the diode leg has a midpoint electrically connected to the neutral terminal (N being neutral terminal connected to midpoint N4 of diode leg 20, when switch RLG=on);
an output filter (an output filter capacitor leg 30 includes series connected output capacitors C1-2 at node N5; wherein capacitor leg 30 is connected in parallel with the diode leg 20, when switches RL7=Off), electrically connected in parallel to the diode leg (in parallel with diode leg 20) and comprising two capacitors connected in series (C1-2 connected in series in node N5), wherein the output filter has a midpoint between the two capacitors (the output filter capacitor leg 30 includes series connected output capacitors C1-2 at node N5; wherein capacitor leg 30 is connected in parallel with the diode leg 20, when switches RL7=Off); and
a T-type leg (T-type leg being series-connected two active switches ‘RL6, RL7’, connected between the diode leg 20’s midpoint N4 and the output filter capacitor leg 30’s midpoint N5), connected between the midpoint (midpoint N4) of the diode leg (the diode leg 20’s midpoint N4) and the midpoint (midpoint N5) of the output filter (the output filter capacitor leg 30’s midpoint N5) and comprising two active switches (T-type leg being series-connected switches ‘RL6, RL7’).
Regarding claim 11, Li teaches (Fig. 1-13; Para 24-45) the upper switches and the lower switches of the first switch leg, the second switch leg and the third switch leg (10: parallel connected phase legs ‘11, 12 & 13’; 1st phase leg 11 includes upper switch Q1 connected in series with lower switch Q2 in midpoint N1 corresponding to input terminal VL1N; 2nd phase leg 12 includes upper switch Q3 connected in series with lower switch Q4 in midpoint N2 corresponding to input terminal VL2N’ and 3rd phase leg 13 includes upper switch Q5 connected in series with lower switch Q6 in midpoint N3 corresponding to input terminal VL3N) are configured to operate at greater than 0% duty cycle ratio and less than 100% duty cycle ratio (a duty cycle thereof is, for example, but not limited to, 50%; Para 43, 48-49) .
Regarding claim 12, Li teaches (Fig. 1-13; Para 24-45) the first switch leg, the second switch leg and the third switch leg (10: parallel connected phase legs ‘11, 12 & 13’; 1st phase leg 11 includes upper switch Q1 connected in series with lower switch Q2 in midpoint N1 corresponding to input terminal VL1N; 2nd phase leg 12 includes upper switch Q3 connected in series with lower switch Q4 in midpoint N2 corresponding to input terminal VL2N’ and 3rd phase leg 13 includes upper switch Q5 connected in series with lower switch Q6 in midpoint N3 corresponding to input terminal VL3N) are configured to operate at different duty cycles (a duty cycle thereof is, for example, but not limited to, 50%; Para 43, 48-49), and the first switch leg, the second switch leg and the third switch leg have no phase shift relative to one another.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US Pub 2023/0035838), in view of Sun et al. (“Sun”, US Pub 2021/0296922).
Regarding claim 7, Li teaches a plurality of elements (i.e., 40), wherein first terminals of each of the plurality of elements being electrically connected between (i.e., one (i.e., 1st) of the plurality of element’s one terminal connected between input terminal A and L1’s input end terminal of phase leg 100; another one (i.e., 2nd) of the plurality of element’s one terminal connected between input terminal B and L2’s input end terminal of phase leg 200; and another one (i.e., 3rd) of the plurality of element’s one terminal connected between input terminal C and L3’s input end terminal of phase leg 300) the corresponding boost inductor of the plurality of boost inductors (input end terminals of each of boost inductors L1-3) and the corresponding input terminal (VLIN, VL2N, VL3N), and the second terminal of each of the plurality elements being coupled to the neutral terminal (N being neutral terminal connected to other terminals of each one of the plurality of elements (i.e., 1st-3rd));
However, Li fails to teach use of plurality of capacitors for the plurality of elements, wherein first terminals of the three capacitors are electrically connected to three phases of the AC power source respectively, and second terminals of the three capacitors are coupled to the neutral terminal.
However, Sun teaches (Para 43-46) use of plurality of capacitors (C1, C2, C3) for the plurality of elements, wherein first terminals of the three capacitors are electrically connected to three phases of the AC power source respectively (C1’s one terminal connected between AC input terminal A and L1’s input end terminal of phase leg 100; C2’s one terminal connected between AC input terminal B and L2’s input end terminal of phase leg 200; and C3’s one terminal connected between AC input terminal C and L3’s input end terminal of phase leg 300), and second terminals of the three capacitors are coupled to the neutral terminal (N being neutral terminal connected to other terminals of each C1-3).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li’s converter to include use of plurality of capacitors for the plurality of elements as respective input filters, wherein first terminals of the three capacitors are electrically connected to three phases of the AC power source respectively, and second terminals of the three capacitors are coupled to the neutral terminal, as disclosed by Sun, as doing so would have reduced or suppressed any unwanted input noise developing towards high-efficiency, high power density, high-reliability, lower cost and volumed power supply circuit or modules, as taught by Sun (Para 2-4 and abstract).
Regarding claim 8, Li teaches an input limiting circuit (resistor R1 and switches ‘RL1-4, RL8-9’) electrically connected with the three input terminals (VLIN, VL2N, VL3N) and configured to limit the single-phase input (Para 30).
However, Li fails to explicitly teach use of an input filter circuit (for the limiting circuit) to filter electrically connected with the three input terminals and configured to filter the single-phase input.
However, Sun explicitly teaches (Para 43-46) use of an input filter circuit (C1, C2, C3) to filter electrically connected with the three input terminals and configured to filter the single-phase input (C1’s one terminal connected between AC input terminal A and L1’s input end terminal of phase leg 100; C2’s one terminal connected between AC input terminal B and L2’s input end terminal of phase leg 200; C3’s one terminal connected between AC input terminal C and L3’s input end terminal of phase leg 300; and N being neutral terminal connected to other terminals of each C1-3).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Li’s converter to include use of plurality of capacitors for the plurality of elements as respective input filters, wherein first terminals of the three capacitors are electrically connected to three phases of the AC power source respectively, and second terminals of the three capacitors are coupled to the neutral terminal, as disclosed by Sun, as doing so would have reduced or suppressed any unwanted input noise developing towards high-efficiency, high power density, high-reliability, lower cost and volumed power supply circuit or modules, as taught by Sun (Para 2-4 and abstract).
Allowable Subject Matter
Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 9, Li teaches a control system (50) configured to perform the method, wherein the method comprises: controlling the two active switches … AC voltage … power factor operation (control system 50 alternatively or switches off T-type leg’s series-connected two active switches ‘RL6, RL7’, which is connected between the diode leg 20’s midpoint N4 and the output filter capacitor leg 30’s midpoint N5. However, control system is silent or does not teach about switching on both two active switches ‘RL6, RL7’ around AC voltage zero crossings during non-unity power factor operation. For reference, see Applicant’s Spec Para 19-20, 41-42, 46-47, 48*, 59, 65-66, 70, 74, 76).
However, none of the cited art(s) failed to teach, as a whole, nor would it be obvious to piecewise combine with any other arts, the following limitations(s), a control system, wherein the control system is configured to “turn on the two active switches of the T-type leg around AC voltage zero crossings during non-unity power factor operation (about switching on both two active switches of the claimed T-Type Leg around AC voltage zero crossings during non-unity power factor operation. For reference, see Applicant’s Spec Para 19-20, 41-42, 46-47, 48*, 59, 65-66, 70, 74, 76; and in combination with specific connections between each and every element)”.
Claim 10 depends on claim 9.
Claims 1-5 are allowed.
Regarding independent claims 1, Li et al. (“Li”, US Pub 2023/0035838) teaches (Fig. 1-13; Para 24-45) a method of operating a totem-pole power factor correction converter (Fig. 1), comprising:
three input terminals (VLIN, VL2N, VL3N), a neutral terminal (N), and two output terminals (Vo+, Vo-);
a plurality of phase legs (10: parallel connected phase legs ‘11, 12 & 13’) connected with each other in parallel, wherein each of the plurality of phase legs (each phase legs 11-13) comprises an upper switch and a lower switch connected in series, and has a midpoint between the upper switch and the lower switch, wherein the midpoint of each of the plurality phase legs is connected with the corresponding input terminal of the three input terminals (phase leg 11 includes upper switch Q1 connected in series with lower switch Q2 in midpoint N1 corresponding to input terminal VL1N; phase leg 12 includes upper switch Q3 connected in series with lower switch Q4 in midpoint N2 corresponding to input terminal VL2N’ and phase leg 13 includes upper switch Q5 connected in series with lower switch Q6 in midpoint N3 corresponding to input terminal VL3N);
a plurality of boost inductors (boost inductors L1-3), wherein each of the plurality of boost inductors is connected between the corresponding input terminal of the three input terminals and the midpoint of the corresponding phase leg of the plurality of phase legs (boost inductor L1 connected between input terminal VLIN and midpoint N1 of phase leg 11; boost inductor L2 connected between input terminal VL2N and midpoint N2 or phase leg 2; and boost inductor L2 connected between input terminal VL3N and midpoint N3 of phase leg 3);
a plurality of elements (i.e., 40), wherein one terminal of each of the plurality of capacitors is connected between (i.e., one (i.e., 1st) of the plurality of element’s one terminal connected between input terminal A and L1’s input end terminal of phase leg 100; another one (i.e., 2nd) of the plurality of element’s one terminal connected between input terminal B and L2’s input end terminal of phase leg 200; and another one (i.e., 3rd) of the plurality of element’s one terminal connected between input terminal C and L3’s input end terminal of phase leg 300) the corresponding boost inductor of the plurality of boost inductors (input end terminals of each of boost inductors L1-3) and the corresponding input terminal (VLIN, VL2N, VL3N), and the other terminal of each of the plurality capacitors is connected to the neutral terminal (N being neutral terminal connected to other terminals of each one of the plurality of elements (i.e., 1st-3rd));
a diode leg (diode leg 20 connected in parallel with phase legs 11-13; wherein diode leg 20 includes series connected D1-2 at midpoint N4; and N being neutral terminal connected to midpoint N4 of diode leg 20, when switch RLG=on) connected with the plurality of phase legs (phase legs 11-13) in parallel (diode leg 20 connected in parallel with phase legs 11-13) and comprising two diodes (D1-2) connected in series (D1-2 connected in series at a midpoint N4), wherein the diode leg (diode leg 20) has a midpoint (midpoint N4) between the two diodes (D1-2), and the midpoint (midpoint N4) of the diode leg (diode leg 20) is connected with the neutral terminal (N being neutral terminal connected to midpoint N4 of diode leg 20, when switch RLG=on);
an output filter (an output filter capacitor leg 30 includes series connected output capacitors C1-2 at node N5; wherein capacitor leg 30 is connected in parallel with the diode leg 20, when switches RL7=Off) connected with the diode leg in parallel (in parallel with diode leg 20) and comprising two capacitors connected in series (C1-2 connected in series), wherein the output filter has a midpoint between the two capacitors (the output filter capacitor leg 30 includes series connected output capacitors C1-2 at node N5; wherein capacitor leg 30 is connected in parallel with the diode leg 20, when switches RL7=Off);
a T-type leg (T-type leg being series-connected two active switches ‘RL6, RL7’, connected between the diode leg 20’s midpoint N4 and the output filter capacitor leg 30’s midpoint N5) connected between the midpoint (midpoint N4) of the diode leg (the diode leg 20’s midpoint N4) and the midpoint (midpoint N5) of the output filter (the output filter capacitor leg 30’s midpoint N5) and comprising two active switches connected in series (T-type leg being series-connected switches ‘RL6, RL7’); and
a control system (50) configured to perform the method, wherein the method comprises: controlling the two active switches … AC voltage … power factor operation (control system 50 alternatively or switches off T-type leg’s series-connected two active switches ‘RL6, RL7’, which is connected between the diode leg 20’s midpoint N4 and the output filter capacitor leg 30’s midpoint N5. However, control system is silent or does not teach about switching on both two active switches ‘RL6, RL7’ around AC voltage zero crossings during non-unity power factor operation. For reference, see Applicant’s Spec Para 19-20, 41-42, 46-47, 48*, 59, 65-66, 70, 74, 76).
However, Li fails to teach use of plurality of capacitors for the plurality of elements, wherein one terminal of each of the plurality of capacitors is connected between the corresponding boost inductor of the plurality of boost inductors and the corresponding input terminal, and the other terminal of each of the plurality capacitors is connected to the neutral terminal; and a control system configured to perform the method, wherein the method comprises: turning the two active switches on around AC voltage zero crossings during non-unity power factor operation (about switching on both two active switches of the claimed T-Type Leg around AC voltage zero crossings during non-unity power factor operation. For reference, see Applicant’s Spec Para 19-20, 41-42, 46-47, 48*, 59, 65-66, 70, 74, 76; and in combination with specific connections between each and every element).
However, Sun et al. (“Sun”, US Pub 2021/0296922) teaches a plurality of capacitors (C1, C2, C3), wherein one terminal of each of the plurality of capacitors is connected between the corresponding boost inductor of the plurality of boost inductors (L1, L2, L3) and the corresponding input terminal (C1’s one terminal connected between input terminal A and L1’s input end terminal of phase leg 100; C2’s one terminal connected between input terminal B and L2’s input end terminal of phase leg 200; and C3’s one terminal connected between input terminal C and L3’s input end terminal of phase leg 300), and the other terminal of each of the plurality capacitors is connected to the neutral terminal (N being neutral terminal connected to other terminals of each C1-3).
However, none of the cited art(s) failed to teach, as a whole, nor would it be obvious to piecewise combine with any other arts, the following limitations(s),
a control system configured to perform the method, wherein the method comprises: “turning the two active switches on around AC voltage zero crossings during non-unity power factor operation (about switching on both two active switches of the claimed T-Type Leg around AC voltage zero crossings during non-unity power factor operation. For reference, see Applicant’s Spec Para 19-20, 41-42, 46-47, 48*, 59, 65-66, 70, 74, 76; and in combination with specific connections between each and every element)”; and similarly
Claims ‘2-5’ depending on claim 1.
Conclusion
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
