DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because some of the texts shown in at least Figures 3, 4C, 6, and 7 of the drawings are either too small or blurry. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0059], last two lines, the phrase “473 and 473” described in the specification is not clear. As shown in FIG. 4E, it appears to be “472 and 473”.
Appropriate correction is required.
Claim Objections
Claims 22, 23, 26, and 30-40 objected to because of the following informalities:
22. (Proposed Amendment) The method of claim 21, wherein the clock signal operates at a clock frequency and a single frequency is equal to the clock frequency.
23. (Proposed Amendment) The method of claim 21, wherein the differential output signal is a pulse amplitude modulation 4-level (PAM-4) radio frequency (RF) serializer deserializer (SerDes) signal.
26. (Proposed Amendment) The method of claim 21, wherein the transmitting occurs over printed circuit board (PCB) traces.
30. (Proposed Amendment) The method of claim 21, wherein the generating [[a]] the pair of currents from the pair of digital values comprises converting, by a differential current digital-to-analog converter, the pair of digital values into differential analog currents.
31. (Proposed Amendment) The method of claim 21, further comprising:
receiving the differential output signal;
generating a plurality of pairs of currents based on the differential output signal;
generating [[a]] the plurality of outputs based on the plurality of pairs of currents; and
generating the clock signal and the two-bit data signal.
32. (Proposed Amendment) The method of claim 31, wherein the clock signal operates at a clock frequency and a single frequency is equal to the clock frequency.
40. (Proposed Amendment) The method of claim 31, wherein the generating [[a]] the pair of currents from the pair of digital values comprises converting, by a differential current digital-to-analog converter, the pair of digital values into differential analog currents.
Claims 33-38 depend either directly or indirectly from claim 31, therefore they are also objected.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22 and 32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 22 and 32 depend directly or indirectly on claim 21. However, the phrase "... and single frequency is equal to the clock frequency," recited in both claims, is indefinite. Claim 21 recites a "single frequency pulse amplitude modulation signal," making it unclear if the "single frequency" in claims 22 and 32 refers to this signal. Clarification is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-23, 25-33, and 35-40 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LI et al. (US 2025/0233567 A1), hereinafter “Li”.
Li illustrates a system 100 in FIG. 1A which data is transmitted from a transmitter 110 to a receiver 116 across a channel 120 (e.g., a serial link) coupled between the transmitter 110 and the receiver 116. In this example, the channel 120 is a differential channel (e.g., a differential serial link) including a first transmission line 122 and a second transmission line 124 configured to carry a differential signal. The transmitter 110 receives bits from a data source (not shown) and transmits the bits as a sequence of symbols across the channel 120. In the example in FIG. 1A, the transmitter 110 has a differential output including a first output 112 and a second output 114, and transmits each symbol via the differential output using differential signaling. In this example, the voltage level (i.e., amplitude) of each symbol may correspond to the voltage between the first output 112 and the second output 114. As discussed further below, the transmitter 110 may transmit data using pulse amplitude modulation 4-level (PAM-4) where each symbol carries two bits. The receiver 116 receives the symbols from the channel 120 and converts the received symbols into bits. The receiver 116 may send the bits to another circuit for further processing. In the example in FIG. 1A, the receiver 116 is coupled to a deserializer 150 to support serializer/deserializer (SerDes) communication across the channel 120. In this example, the deserializer 150 receives the bits from the receiver 116 and outputs the bits in parallel bit streams to a processor (not shown) or another circuit. See more detail discussed in paragraphs [00180 to [0026].
Li further teaches in paragraph [0030] that the DFE 140 of the receiver 116 includes a first section 305 and a second section 308, in which operations of the first section 305 and the second section 308 are timed using a clock signal Clk having a frequency that is half the frequency of the incoming symbols.
Regarding claim 21, as shown in FIG. 1A and discussed in at least paragraphs [0018] to [0026], and [0030], it is inherent and well-known in the art of digital communication and integrated circuit design to perform the method of claim 21. It forms the foundational operating principle for digital-to-analog converters (DACs) used in high-speed SerDes (Serializer/Deserializer) transmitters employing Pulse Amplitude Modulation (PAM-4).
The method of claim 21 is standard and ubiquitous in electrical engineering for the following reasons:
1. Two-Bit Data to Pairs of Digital Values
In SerDes systems, transmitters serialize high-speed parallel data into bit-streams. For PAM-4, the system translates incoming data into symbols, where each symbol represents 2 bits (e.g., 00, 01, 10, 11). To generate a PAM-4 symbol, digital logic inherently groups the data bits into digital pairs or thermometer-coded values that correspond to the four distinct voltage levels.
2. Digital Values to Pairs of Currents
Converting digital pairs into currents for transmission utilizes a Current-Mode Logic (CML) or a switched-current DAC architecture. Using current steering, where digital values control binary-weighted or thermometer-coded current sources is the standard way to drive transmission lines. It is preferred because it yields precise voltage swings when terminated by the characteristic impedance of the channel (usually 50 Ohms per trace).
3. Single-Frequency Pulse Amplitude Modulated Signal
To transmit PAM-4 over a differential channel, apply the currents to a first and second transmission line. Differential signaling where the signals are complementary inherently creates a robust, single-frequency pulse amplitude modulated waveform that minimizes common-mode noise and electromagnetic interference (EMI).
4. Transmitting Based on a Clock Signal
At high data rates (e.g., 56 Gbps or 112 Gbps per lane in Ethernet or PCIe standards), it becomes difficult to run transmitter/receiver digital logic at the exact symbol rate. Therefore, utilizing half-rate clocking where the clock frequency is half the symbol rate is a widely used, classic technique. By leveraging both the rising and falling edges (or using an interleaved architecture) of a half-rate clock, the transmitter and the receiver's Decision Feedback Equalizer (DFE) can correctly process symbols without pushing internal circuitry to unsustainable speeds.
Regarding claims 22 and 32, as described in claim 21 above, it is inherent and well-known in the art that “the clock signal operates at a clock frequency” and “a single frequency is equal to the clock frequency” based on these concepts relate to standard SerDes and DFE architectures:
1. A single frequency is equal to the clock frequency
This is considered inherent by definition. By mathematical identity, a single frequency (f1) is always equal to itself (f1 = f1).
2. operating at a clock frequency
It is also well-known and inherent. Any clocked digital circuit or mixed-signal system (such as the DFE, serializer, or deserializer) fundamentally requires a clock signal to trigger its operations. By definition, that clock signal operates at a specific frequency.
3. Full-Rate vs. Half-Rate Clocks
The nuance of clocking in serializer/deserializer (SerDes) communication and Decision Feedback Equalizers (DFEs) generally revolves around whether the circuit runs on a full-rate clock or a half-rate clock:
Full-Rate (Symbol-Rate) Clock: In this architecture, the clock frequency equals the symbol rate (or baud rate) of the incoming signal.
Half-Rate Clock: In your system description, you noted that the DFE is timed using a clock signal that is half the frequency of the incoming symbols. This is a very well-known, power-saving architecture in high-speed SerDes designs. Because DFE circuits have notoriously tight timing budgets (especially for the first tap), dividing the clock rate by two gives the adder logic and feedback loops twice as much time to compute the correct equalization, easing hardware design.
Regarding claims 23 and 33, as described in claim 21 above, wherein the differential output signal is a PAM-4RF SerDes signal.
Regarding claims 25-26 and 35-36, the transmission occurring over wires or over printed circuit board (PCB) traces is both inherent and well-known in the art of high-speed SerDes (Serializer/Deserializer) communications. Using differential transmission lines alongside DFE equalization and SerDes strongly implies that the system is an electrical wireline communication link as shown in FIG. 1A. Thus, transmission over physical wires or PCB traces is a fundamental assumption and inherent requirement in this technical field.
Regarding claims 27-28 and 37-38, as described in claim 21 above, the described mechanism is well known in the art of SerDes (Serializer/Deserializer) communications and high-speed signaling, it is a standard design choice in the industry:
Half-Rate Clocking is Standard: Operating a receiver's Decision Feedback Equalizer (DFE) with a half-rate clock signal (a clock where the frequency is half of the symbol/baud rate) is an industry-standard technique. It resolves high-frequency timing bottlenecks in CMOS circuits by processing two bits (or symbols) per full clock cycle.
Serialization & Deserialization: A SerDes system is explicitly designed to translate between parallel (e.g., N-bit streams) and serial data. Using the high and low phases of a clock cycle (often referred to as Double Data Rate or DDR signaling) is the foundational mechanism used by serializers to transmit sequential bits and by deserializers to reconstruct parallel streams.
Regarding claims 29 and 39, receiving a valid signal indicating whether the data is valid in high-speed SerDes is inherent and well known in the art. It is fundamental for link initialization, training, flow control, and preventing the processing of junk data before a connection is fully established. Further, the specific mechanism of validating, accepting, and discarding data based on a flag is a foundational principle of digital communications, data framing, and error-control. The concepts of validation checks (first value for valid, second value for invalid) and conditional execution (accepting/discarding) are core tenets of digital logic design, SerDes physical layer (PHY) processing, and differential signaling. Building a receiver that ignores erroneous data or idles ensures system stability.
Regarding claim 30 and 40, the step of converting digital values into differential analog currents using a differential current-mode digital-to-analog converter (DAC) is well known in the art. For example, in a DFE receiver as shown in FIG. 1A, the system cancels out inter-symbol interference (ISI) by predicting the error and subtracting it. Converting digital tap weights into analog currents using a DAC allows the receiver to seamlessly inject or subtract these precise correction currents at the receiver's summing node without disrupting the clock signal or voltage thresholds of the samplers.
Regarding claim 31, as described in claim 21 above, the described architecture and operations of FIG. 1A as recited in claim 31 are well-known in the art of high-speed SerDes (Serializer/Deserializer) and communications engineering for the following reasons:
1. Receiving the Differential Signal
Why it’s standard: Differential signaling transmits complementary signals across two lines (Vdiff = V+ - V-). This cancels out common-mode electromagnetic noise and interference. It is the cornerstone of robust, high-speed data transmission in modern buses and SerDes links.
2. Generating Pairs of Currents & Outputs Based on the Currents
Why it’s standard: In high-speed receiver front-ends (such as continuous-time linear equalizers or transimpedance amplifiers), incoming voltage waveforms are typically converted to currents to perform linear operations. Generating multiple pairs of currents allows the receiver to weight them differently. For instance, this is how a Decision Feedback Equalizer (DFE) taps and subtracts post-cursor inter-symbol interference (ISI) from the incoming signal.
3. Generating the Clock Signal and the Two-Bit Data Signal (PAM-4)
Why it’s standard: In PAM-4 (Pulse Amplitude Modulation 4-level), a symbol has 4 distinct voltage levels to carry 2-bits of information per symbol. To decode this, the receiver uses multiple comparators (slicers) that generate partial outputs and logically map them into a two-bit data signal.
For the clock, a Clock and Data Recovery (CDR) circuit inherently generates a synchronized clock signal from the incoming data stream to properly sample the symbols.
Further, in high-speed receivers, operating the DFE sections at half the frequency (half-rate clock) of the incoming symbols is a well-known design technique used to overcome hardware speed limitations. It utilizes parallel processing architectures (like 1-to-2 demultiplexing or unrolled DFEs) so that the slower analog logic has a full symbol period to evaluate and settle, while maintaining ultra-high throughput.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 24 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Li.
Regarding claim 24 as applied to claim 21 and claim 34 as applied to claim 31, although Li describes the differential output signal is a PAM-4 RF SerDes signal, but fails to show or teach that the differential output signal is a PAM-8 RF SerDes signal.
In order to Increased Bits Per Symbol, by definition, PAM-4 uses 22 = 4 distinct amplitude levels to transmit 2 bits per symbol, for PAM-8, the system’s transmitter and receiver are configured to resolve 23 = 8 distinct voltage levels, allowing each symbol to carry 3 bits of data instead of 2. However, by mapping data to 8 distinct levels, the system achieves a 50% increase in data throughput per Hertz of bandwidth. A PAM-8 SerDes transmits 3 bits per cycle, significantly increasing the overall bitrate without requiring a wider RF channel bandwidth. Further, by Matching Clock-to-Data Ratios, as point out by Li that the half-rate clock signal (Clk) operates efficiently over this setup. Since PAM-8 packs more bits into the same symbol transition interval, the processing throughput multiplies even though the symbol clock remains half the frequency of the incoming/outgoing bits.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art as taught by Li that SerDes (Serializer/Deserializer) links are typically bandwidth-limited by the channel. By shifting from PAM-4 to PAM-8 is a way to push 50% more data through the exact same channel without modifying the physical transmission lines in order to increase data throughput by 50% without increasing the baud rate (channel bandwidth).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zerbe et al. relates to a multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the one or more symbols are driven at a symbol rate, the symbol rate selected in accordance with the PAM mode signal so that a data rate of the driven symbols in constant with respect to changes in the state of the PAM mode signal.
Chada et al. relates to a serial data channel includes a transmitter that encodes serial data using a quaternary PAM-4 scheme, wherein the four PAM-4 signal levels include two balanced pairs of differential signal levels. The channel includes a de-emphasis circuit that determines that first and second symbols are in a first PAM-4 state, that a third symbol is in a second PAM-4 state, and provides a first de-emphasis to a voltage level of the second symbol in response to determining that the third symbol is represented as the second state. The de-emphasis circuit further determines that fourth and fifth symbols are in the second state, that a sixth symbol is in the first state, and provides a second de-emphasis to a voltage level of the fifth symbol in response to determining that the sixth symbol is represented as the first state.
LEE et al. relates to a data communication apparatus has a plurality of line drivers configured to couple the apparatus to a 3-wire link, and a data encoder configured to encode at least 3 bits of binary data in each transition between two symbols that are consecutively transmitted by the plurality of line drivers over the 3-wire link such that each pair of consecutively-transmitted symbols comprises two different symbols. Each symbol defines signaling states of the 3-wire link during an associated symbol transmission interval such that each wire of the 3-wire link is in a different signaling state from the other wires of the 3-wire link during the associated symbol transmission interval. Data may be encoded using a combination of 3-phase and pulse amplitude modulation.
Groen et al. relates to a current-mode transmitter amplifies a differential input signal to a differential, current-mode output signal. A split-input, current-mode-logic stage produces small, analog signals to limit switching currents and thus power consumption and power-supply noise. These small, analog signals are driven through a source-follower stage to reduce loading and shift the common-mode voltage to a desired level. A switched-current-source H-bridge driver combines differential outputs from the source-follower stage to provide an amplified differential output current. The output swing from the H-bridge driver is controlled by the voltage level from the source follower and derived from a replica-bias structure.
Ang et al. relates to a mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.
Hanenschild et al. relates to an apparatus includes a first cascode amplifier that receives as input positive and negative differential outputs of a DAC and provides a positive amplified output and a negative amplified output, and a second cascode amplifier having a positive input and a negative input. The positive input of the second cascode amplifier being coupled to the positive amplified output of the first cascode amplifier. The second cascode amplifier is configured to generate a positive amplified current and a negative amplified current at a negative amplified output. The positive amplified current and the negative amplified current are combined and a resulting output current is provided as input to an anode of the laser. A transformer is coupled between the negative amplified output of the first cascode amplifier and the negative input of the second cascode amplifier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Young T. Tse whose telephone number is (571)272-3051. The examiner can normally be reached Mon-Fri 10:30am-7pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh M Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Young T. Tse/Primary Examiner, Art Unit 2632
Prosecution Insights