DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lercari (US 11175984 B1) in view of O'Connor (US 2020/0097359 A1) in view of Emerson (US 2022/0232075 A1) in view of Jadon (US 10552058 B1).
In regards to claim 1, Lercari teaches:
A memory system comprising: a nonvolatile memory chip; and a controller that controls the nonvolatile memory chip, wherein the controller is configured to store, in a first storage unit of the nonvolatile memory chip, (25, This disclosure provides techniques for facilitating and/or providing additional redundancy for data stored in asymmetric non-volatile memory (“ANVM”) structures. In one embodiment, the ANVM is flash memory such as implemented by one or more chips of NAND flash memory, formed as part of a solid-state drive (“SSD,” or simply “drive”) having a dedicated memory controller; the memory controller can be an integrated circuit primarily concerned with controlling the operation of one or more chips of NAND flash memory (i.e., a “memory controller integrated circuit” for NAND flash memory).)
Lercari fails to teach:
address translation information for translating a logical address into a physical address and management information for the controller to use in management of operations of the nonvolatile memory chip, for every first cycle, store, in a second storage unit of the nonvolatile memory chip, duplicate information of the address translation information and the management information stored in the first storage unit;
However, O'Connor teaches:
address translation information for translating a logical address into a physical address and management information for the controller to use in management of operations of the nonvolatile memory chip, for every first cycle, store, in a second storage unit of the nonvolatile memory chip, duplicate information of the address translation information and the management information stored in the first storage unit; (46 & 4, it is notoriously well-known with flash memory that the technology has an associated endurance limit that varies according to generation, vendor and design, i.e., typically on the order of hundreds to tens of thousands of write cycles. (e.g., using RAID-style redundancy), as the need for address translation makes linking data and associated EC information.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory controller for asymmetric non-volatile memory of Lercari with the teaching of O'Connor, which teaches a memory buffer device to read and receive data from a memory address and error correction logic in order reduce the impact of errors. (O'Connor: 0020, Embodiments of the present invention provide a common random bit error, or random symbol error, correction scheme that minimizes a performance impact of error checking and correcting, for both memory devices that exhibit high RBERs as well as memory devices that exhibit low RBERs.)
Lercari in view of O'Connor fails to teach:
and determine whether to cause the duplicate information stored in the second storage unit to be exhibited in the first storage unit.
However, Emerson teaches:
and determine whether to cause the duplicate information stored in the second storage unit to be exhibited in the first storage unit. (0041, control information may be stored in multiple locations, that the control information may be stored in multiple locations for purposes of redundancy, for example, or that the control information may otherwise be distributed across multiple memory blocks in the storage drives 171A-F.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory controller for asymmetric non-volatile memory of Lercari with the teaching of Emerson, which teaches a data storage system and a client device communicatively coupled to the data storage device in order improve options for solid-state memories. (Emerson: 0001, many solid-state drives are designed to conform to hard disk drive standards for compatibility reasons, which makes it difficult to provide enhanced features or take advantage of unique aspects of flash and other solid-state memory.)
With regards to claim 2, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 1. Lercari teaches:
wherein, in response to a determination by the controller that a transient error caused by a radioactive ray has occurred, the controller is further configured to cause the duplicate information stored in the second storage unit to be exhibited in the first storage unit. (3, There also exist schemes which store redundancy information across multiple storage units, for example, to permit recovery of contents of one of the multiple storage units should any one of the multiple storage units become unavailable.)
With regards to claim 3, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 2. Lercari in view of O’Conner in view of Emerson fails to teach:
wherein the controller is further configured to determine whether the transient error caused by the radioactive ray occurs at a time length not less than a second cycle that is shorter than the first cycle.
However, Jadon teaches:
wherein the controller is further configured to determine whether the transient error caused by the radioactive ray occurs at a time length not less than a second cycle that is shorter than the first cycle. (75, The depicted architecture permits address translation to be reduced to relatively simple operations that can be implemented using logic gates and lookup tables, that is, in a manner that can be performed extremely fast, e.g., on an intra-cycle basis (i.e., in less than a clock cycle) or at most using only a handful of clock cycles.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory controller for asymmetric non-volatile memory of Lercari with the teaching of Jadon, which teaches a memory controller for nonvolatile memory by a host in connection with write data in order improve speed and performance. (Jadon: 4, Techniques are needed for improving the performance of nonvolatile memory, including memory characterized by one or more of the characteristics referenced above; as noted, such improvement would increase the ability to use such nonvolatile memory as a substitute for RAM.)
With regards to claim 4, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 3. Lercari in view of O’Conner in view of Emerson fails to teach:
wherein the controller is further configured to determine whether the transient error caused by the radioactive ray occurs at the time length that is not less than the second cycle and also shorter than the first cycle.
However, Jadon teaches:
wherein the controller is further configured to determine whether the transient error caused by the radioactive ray occurs at the time length that is not less than the second cycle and also shorter than the first cycle. (75, The depicted architecture permits address translation to be reduced to relatively simple operations that can be implemented using logic gates and lookup tables, that is, in a manner that can be performed extremely fast, e.g., on an intra-cycle basis (i.e., in less than a clock cycle) or at most using only a handful of clock cycles.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory controller for asymmetric non-volatile memory of Lercari with the teaching of Jadon, which teaches a memory controller for nonvolatile memory by a host in connection with write data in order improve speed and performance. (Jadon: 4, Techniques are needed for improving the performance of nonvolatile memory, including memory characterized by one or more of the characteristics referenced above; as noted, such improvement would increase the ability to use such nonvolatile memory as a substitute for RAM.)
With regards to claim 5, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 2. Lercari fails to teach:
wherein the controller is further configured to determine whether the transient error caused by the radioactive ray occurs based on communication with a host apparatus.
However, O’Conner teaches:
wherein the controller is further configured to determine whether the transient error caused by the radioactive ray occurs based on communication with a host apparatus. (0024, There also exist schemes which store redundancy information across multiple storage units, for example, to permit recovery of contents of one of the multiple storage units should any one of the multiple storage units become unavailable.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory controller for asymmetric non-volatile memory of Lercari with the teaching of O'Connor, which teaches a memory buffer device to read and receive data from a memory address and error correction logic in order reduce the impact of errors. (O'Connor: 0020, The primary failure modes for contemporary low BER rate memory devices such as the current generation of DDR4 DRAM chips include single cell errors which can manifest themselves as minor hardware defects, and as bit flips due to cosmic rays and alpha particle hits. A background scrubbing mechanism can be used to detect and correct soft errors in the system by reading all address locations looking for soft errors and if it detects an error, the scrubbing attempts to correct it.)
With regards to claim 6, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 5. Lercari teaches:
wherein under a condition the transient error does not occur, and the host apparatus makes an access request to the nonvolatile memory chip for every second cycle, the controller is further configured to determine whether there is the access request from the host apparatus, at a time length not less than the second cycle, and in response to a determination that there is no access request, determine that the transient error caused by the radioactive ray has occurred. (30, “EC information” as used herein refers to information relating to error correction values or the location or existence of error correction values; it for example can encompass single or multi-bit parity values or other forms of error correction codes or data and/or it can encompass an identifier, link or address that points to one or more of these values; as non-limiting examples, it can refer to a result of an XOR operation performed on two pieces of multibit data, or a notification that EC values have been stored in a location (i.e., such that the host or a memory controller for a different drive can then request or access those values).)
With regards to claim 7, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 6. Lercari in view of O’Conner in view of Emerson fails to teach:
wherein the controller is further configured to determine whether there is the access request from the host apparatus at a length not less than the second cycle and transmit a predetermined command to the host apparatus upon determination that there is no access request, and when there is no response to the predetermined command from the host apparatus, determine that the transient error caused by the radioactive ray has occurred.
However, Jadon teaches:
wherein the controller is further configured to determine whether there is the access request from the host apparatus at a length not less than the second cycle and transmit a predetermined command to the host apparatus upon determination that there is no access request, and when there is no response to the predetermined command from the host apparatus, determine that the transient error caused by the radioactive ray has occurred. (44, the memory controller can be configured to delay a write command but allow it to automatically proceed with a write unless an abort command has been received from a host within a predetermined time interval; conversely, a memory controller can be configured to abort a command to write data that duplicates other existing data unless it receives a commit command within the predetermined time interval.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory controller for asymmetric non-volatile memory of Lercari with the teaching of Jadon, which teaches a memory controller for nonvolatile memory by a host in connection with write data in order improve speed and performance. (Jadon: 4, Techniques are needed for improving the performance of nonvolatile memory, including memory characterized by one or more of the characteristics referenced above; as noted, such improvement would increase the ability to use such nonvolatile memory as a substitute for RAM.)
With regards to claim 8, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 5. Lercari teaches:
wherein the controller is configured to store a plurality of times the past duplicate information in the second storage unit, and under a condition there is no access request from the host apparatus, the controller is further configured to read and cause the duplicate information that is most newly stored in the second storage unit to be exhibited in the first storage unit. (3, There also exist schemes which store redundancy information across multiple storage units, for example, to permit recovery of contents of one of the multiple storage units should any one of the multiple storage units become unavailable.)
With regards to claim 9, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 8. Lercari teaches:
wherein the controller is configured to store a plurality of times the past duplicate information in the second storage unit, and under a condition there is no access request from the host apparatus, the controller is further configured to read and cause the duplicate information that is most newly stored in the second storage unit to be exhibited in the first storage unit. (3, There also exist schemes which store redundancy information across multiple storage units, for example, to permit recovery of contents of one of the multiple storage units should any one of the multiple storage units become unavailable.)
With regards to claim 10, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 1. Lercari teaches:
wherein the controller is further configured to store the duplicate information in the second storage unit every time at least one of the address translation information and the management information stored in the first storage unit is updated. (61, There are various circumstances under which this can be quite useful, e.g., for some EC information schemes, delayed processing and/or transmission architecture permits the memory controller to save space, command overhead and/or processing cycles by accumulating redundancy information for many writes prior to sending the information to the host or another drive.)
With regards to claim 11, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 1. Lercari teaches:
wherein, for every first cycle, the controller is further configured to store, in the second storage unit, duplicate information of the address translation information and the management information stored in the first storage unit and user data stored in the nonvolatile memory chip. (61, There are various circumstances under which this can be quite useful, e.g., for some EC information schemes, delayed processing and/or transmission architecture permits the memory controller to save space, command overhead and/or processing cycles by accumulating redundancy information for many writes prior to sending the information to the host or another drive.)
With regards to claim 12, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 11.
Lercari in view of O'Connor fails to teach:
wherein the user data includes at least one of program code of an operation system, program code of application software operated on the operation system, data used for the operation system, and data used for the application software.
However, Emerson teaches:
wherein the user data includes at least one of program code of an operation system, program code of application software operated on the operation system, data used for the operation system, and data used for the application software. (0084, The embodiments depicted with reference to FIGS. 2A-G illustrate a storage cluster that stores user data, such as user data originating from one or more user or client systems or other sources external to the storage cluster. The storage cluster distributes user data across storage nodes;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory controller for asymmetric non-volatile memory of Lercari with the teaching of Emerson, which teaches a data storage system and a client device communicatively coupled to the data storage device in order improve options for solid-state memories. (Emerson: 0001, many solid-state drives are designed to conform to hard disk drive standards for compatibility reasons, which makes it difficult to provide enhanced features or take advantage of unique aspects of flash and other solid-state memory.)
With regards to claim 13, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 1. Lercari teaches:
wherein the nonvolatile memory chip has a third storage unit in which firmware that controls the controller is stored, and the controller is further configured to read and execute the firmware stored in the third storage unit, as part of initialization or reset of the nonvolatile memory chip. (56, Per numeral 375, the drive experiencing the error (“SSD1”) sends an error message to the host (or a drive which stores cross-drive redundancy information); as a response, firmware operating on the receiving processor begins a process of rebuilding the data and/or missing error recovery information.)
With regards to claim 14, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 13. Lercari teaches:
wherein, when reading the firmware stored in the third storage unit, the controller is further configured to read the address translation information and the management information stored in the first storage unit to execute the firmware. (54, a host might add the reported address to its virtual address translation tables so as to direct read requests to the pertinent data at the pertinent drive, zone, VBD, etc.)
With regards to claim 15, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 13.
Lercari in view of O'Connor fails to teach:
wherein the controller is further configured to reset the nonvolatile memory chip after the duplicate information stored in the second storage unit is caused to be exhibited in the first storage unit.
However, Emerson teaches:
wherein the controller is further configured to reset the nonvolatile memory chip after the duplicate information stored in the second storage unit is caused to be exhibited in the first storage unit. (0041, control information may be stored in multiple locations, that the control information may be stored in multiple locations for purposes of redundancy, for example, or that the control information may otherwise be distributed across multiple memory blocks in the storage drives 171A-F.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory controller for asymmetric non-volatile memory of Lercari with the teaching of Emerson, which teaches a data storage system and a client device communicatively coupled to the data storage device in order improve options for solid-state memories. (Emerson: 0001, many solid-state drives are designed to conform to hard disk drive standards for compatibility reasons, which makes it difficult to provide enhanced features or take advantage of unique aspects of flash and other solid-state memory.)
With regards to claim 16, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 13. Lercari teaches:
wherein the controller further includes a fourth storage unit that stores the firmware that is read from the third storage unit, and a fifth storage unit that stores the address translation information and the management information read from the first storage unit, and circuitry structures of the fourth storage unit and the fifth storage unit exhibit a higher susceptibility to a transient error caused by a radioactive ray than a structure of the nonvolatile memory chip. (56, Per numeral 375, the drive experiencing the error (“SSD1”) sends an error message to the host (or a drive which stores cross-drive redundancy information); as a response, firmware operating on the receiving processor begins a process of rebuilding the data and/or missing error recovery information.)
With regards to claim 17, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 16. Lercari teaches:
wherein each of the fourth storage unit and the fifth storage unit is an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory), and the nonvolatile memory chip is a flash memory. (59, The memory controller tracks subdivision-specific metadata using internal storage 411. In one embodiment, this storage can be volatile memory such as synchronous random-access memory (SRAM) or other internal RAM;)
With regards to claim 18, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 16. Lercari in view of O'Connor fails to teach:
wherein, when determining that the transient error caused by the radioactive ray occurs, the controller is further configured to perform a power supply reset operation that erases memory contents of the fourth storage unit and the fifth storage unit, determine whether the transient error is solved afterward, and upon a determination that the transient error is not solved, cause the duplicate information stored in the second storage unit to be exhibited in the first storage unit.
However, Emerson teaches:
wherein, when determining that the transient error caused by the radioactive ray occurs, the controller is further configured to perform a power supply reset operation that erases memory contents of the fourth storage unit and the fifth storage unit, determine whether the transient error is solved afterward, and upon a determination that the transient error is not solved, cause the duplicate information stored in the second storage unit to be exhibited in the first storage unit. (0263, the erasure coding functions are performed mostly or entirely in the storage units 152, which frees up the computing power of the storage nodes 150.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory controller for asymmetric non-volatile memory of Lercari with the teaching of Emerson, which teaches a data storage system and a client device communicatively coupled to the data storage device in order improve options for solid-state memories. (Emerson: 0001, many solid-state drives are designed to conform to hard disk drive standards for compatibility reasons, which makes it difficult to provide enhanced features or take advantage of unique aspects of flash and other solid-state memory.)
With regards to claim 19, Lercari in view of O’Conner in view of Emerson teaches the memory system of claim 1. Lercari teaches:
wherein, when at least one of the address translation information and the management information is updated, the controller is further configured to store at least one of updated address translation information and updated management information in the first storage unit. (87, It could be that this data is new write data (e.g., nothing has yet been stored at these logical addresses 1-6) or that the data represents an overwrite of one or more of logical addresses 1-6 with updated data, with some or none of the data potentially remaining unchanged relative to an earlier write. a SSD used to store EC information.)
With regards to claim 20, Lercari in view of O’Conner in view of Emerson teaches the information processing system and corresponds to claim 1 as analyzed accordingly.
With regards to claim 21, Lercari in view of O’Conner in view of Emerson teaches the information processing system of claim 20. Lercari teaches:
comprising a power supply management apparatus having circuitry configured to control initialization of the memory system, wherein the host apparatus is configured to instruct the power supply management apparatus to initialize the memory system under a condition the controller determines a transient error caused by a radioactive ray has occurred, the nonvolatile memory chip has a third storage unit that stores firmware that upon execution by the controller configures the controller to perform control operations, and in response to the nonvolatile memory chip being initialized via control of the power supply management apparatus, the controller is further configured to read and execute the firmware stored in the third storage unit after the duplicate information stored in the second storage unit is caused to be exhibited in the first storage unit. (3, There also exist schemes which store redundancy information across multiple storage units, for example, to permit recovery of contents of one of the multiple storage units should any one of the multiple storage units become unavailable.)
With regards to claim 22, Lercari in view of O’Conner in view of Emerson teaches the information processing system of claim 20. Lercari teaches:
wherein the memory system is arranged in a low orbit zone. (54, a host might add the reported address to its virtual address translation tables so as to direct read requests to the pertinent data at the pertinent drive, zone, VBD, etc.)
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
Alrod (US 2022/0230685 A1): A storage apparatus includes non-volatile memory cells formed on a memory die, each memory cell configured to hold bits of data, and a control circuit. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data. To improve the accuracy of recovering the encoded foggy phase data, techniques are presented to calibrate the voltage levels used in sensing the foggy state distributions
Nair (US 2018/0157860 A1): Examples of systems described herein include a file server virtual machine of a virtualized file server configured to manage storage of a plurality of storage items. The file server virtual machine including a file system configured to receive an access request directed to a storage item of the plurality of storage items and associated with a user. The file system is further configured to retrieve an access control list having permissions information associated with the storage item, and to cache a permissions profile for the user including all permissions pertaining to the user for the storage item. The file system is further configured to determine whether the access request is permissible based on the cached permissions profile.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to VICTOR PERRY whose telephone number is (571)272-6319. The examiner can
normally be reached Monday - Friday 8:00 - 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor,
Mark Featherstone can be reached on (571) 270-3750. The fax phone number for the organization
where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from
Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit
https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and
https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional
questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like
assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/ Primary Examiner, Art Unit 2111
8/18/2026
Prosecution Insights