DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5 and 12 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Watrous et al (US Patent No. 5532635).
Regarding claim 1, Watrous teaches a pre-charge circuit for a direct current (DC) bus (i.e., pre-charge circuit) (fig. 4), the pre-charge circuit comprising: a varistor (80); a bypass circuit (90, 86, 96, 94) configured to receive a current in response to the DC bus charging (implicit, as seen in fig. 4); a solid-state switch (84) in series with the varistor, with a common node (i.e., common/junction node of MCT-84 and varistor 82) electrically coupled therebetween, wherein the solid-state switch is configured to selectively couple the varistor with the DC bus in response to the bypass circuit receiving the current (implicit, as seen in fig. 4); and a voltage divider circuit (92, 88) coupled with the DC bus and to the common node, wherein the voltage divider circuit is configured to divide a voltage of the DC bus between the varistor and the solid-state switch (implicit, as seen in fig. 4) (e.g., Current through the resistor 88 discharges the capacitor 94. The amount of the current through the resistor 92 is selected to be less than the holding current of the SCR 86. The value of the resistor 88 is selected to pass several times the current that flows through the second resistor 92; Col. 3 lines 53+).
Regarding claim 2, Watrous teaches the pre-charge circuit of claim 1, wherein: the voltage divider circuit is further configured to divide the voltage of the DC bus between the varistor and the solid-state switch based on a target leakage current (i.e., leakage current; Col. 3 lines 53+) for the varistor when the DC bus is charged (e.g., The charge in the capacitor 94 keeps the MCT 84 on for a finite time (longer than the voltage surge). Thus, the surge is absorbed by the varistors 80, 82 while the MCT is on; Col. 3 lines 53+).
Regarding claim 5, Watrous teaches the pre-charge circuit of claim 1, wherein: the current terminates in response to the DC bus being charged (i.e., The charge in the capacitor 94 keeps the MCT 84 on for a finite time (longer than the voltage surge). Thus, the surge is absorbed by the varistors 80, 82 while the MCT is on; Col. 3 lines 53+), and the solid-state switch is further configured to uncouple the varistor from the DC bus in response to at least one of the current terminating and a current through the solid-state switch falling below a threshold current (e.g., Thus, as the capacitor 94 discharges, the current through the SCR 86 will decrease below its holding value and the SCR 86 will turn off, switching off the MCT 84; Col. 3 lines 53+).
Regarding claim 12, Watrous teaches the pre-charge circuit of claim 1, wherein the varistor is configured to clamp at least one transient voltage on the DC bus generated in response to the DC bus charging (implicit, as seen in fig. 4) (e.g., When the voltage across the terminals 1, 2 transiently exceeds the breakdown voltage of the Zener diode 90, the SCR 86 is gated on, which in turn, gates on the MCT 84; Col. 3 lines 53+).
Allowable Subject Matter
Claims 3-4 and 6-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, Watrous teaches the invention set forth above. However, Watrous does not particularly teach wherein: the target leakage current for the varistor is less than about one hundred microamps.
Hence claim 3 will be deemed allowable if rewritten in an independent form.
Regarding claim 4, Watrous teaches the invention set forth above. However, Watrous does not particularly teach wherein the voltage divider circuit comprises: a first resistor in parallel with the varistor and the bypass circuit; and a second resistor in series with the first resistor and in parallel with the solid-state switch.
Hence claim 3 will be deemed allowable if rewritten in an independent form.
Regarding claim 6, Watrous teaches the invention set forth above. However, Watrous does not particularly teach wherein the bypass circuit comprises: a capacitor; and a resistor in series with the capacitor.
Hence claim 6 will be deemed allowable if rewritten in an independent form.
Claims 7-9 depend on objected claim 6, consequently claims 7-9 will also be deemed allowable.
Regarding claim 10, Watrous teaches the invention set forth above. However, Watrous does not particularly teach wherein the solid-state switch comprises a plurality of solid-state switches coupled in series with each other.
Hence claim 10 will be deemed allowable if rewritten in an independent form.
Regarding claim 11, Watrous teaches the invention set forth above. However, Watrous does not particularly teach wherein the varistor comprises a plurality of varistors coupled in parallel with each other.
Hence claim 11 will be deemed allowable if rewritten in an independent form.
Claims 13-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 13, Watrous et al (US Patent No. 5532635) substantially teaches the claim limitations as indicated in claim 1. However, Watrous does not teach or suggest a power distribution system, comprising: a voltage converter configured to selectively couple to a voltage source, and in response thereto, to charge a direct current (DC) bus of the voltage converter to a target voltage; and a pre-charge circuit coupled in parallel with the DC bus, the pre-charge circuit comprising: a varistor; a bypass circuit configured to receive a current in response to charging the DC bus; a solid-state switch in series with the varistor, with a common node electrically coupled therebetween, wherein the solid-state switch is configured to selectively couple the varistor with the DC bus in response to the bypass circuit receiving the current, and to clamp transient voltages on the DC bus that exceed the target voltage by a threshold voltage; and a voltage divider circuit coupled with the DC bus and to the common node, wherein the voltage divider circuit is configured to divide the target voltage of the DC bus between the varistor and the solid-state switch.
Claims 14-18 are allowed, as they depend on allowed claim 13.
Regarding claim 19, Watrous et al (US Patent No. 5532635) substantially teaches the claim limitations as indicated in claim 1. However, Watrous does not teach or suggest a pre-charge circuit for a direct current (DC) bus of a voltage converter, the pre-charge circuit comprising: a first resistor and a second resistor coupled in series between a first terminal and a second terminal of the DC bus, with a common node electrically coupled between the first resistor and the second resistor, wherein a voltage between the first terminal and the second terminal comprises a DC bus voltage; at least one varistor coupled in parallel between the first terminal and the common node; at least one solid-state switch coupled in series between the common node and the second terminal; and a capacitor and a third resistor coupled in series between the first terminal and the at least one solid-state switch, wherein the capacitor and the third resistor are configured to receive a current from the DC bus in response to the voltage converter charging the DC bus, and wherein the current terminates in response to the DC bus being charged to the DC bus voltage, wherein the first resistor and the second resistor are configured to divide the DC bus voltage between the at least one varistor and the at least one solid-state switch, and wherein the at least one solid-state switch is configured to: couple the common node to the second terminal of the DC bus in response to the capacitor and the third resistor receiving the current; and uncouple the common node from the second terminal of the DC bus in response to at least one of the current terminating and a current through the at least one solid-state switch falling below a threshold current.
Claim 20 is allowed, as it depends on allowed claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270- 1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
