Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-20 recite the variable “N”. While it is defined as a “natural number”, this is not clear since that would include natural numbers that would create invalid results for the claimed “NC2” (e.g. when N = 1).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2023/0396268 A1 to Lim et al (herein referred to as Lim, found in Applicant’s IDS).
Referring to claim 1, Lim discloses a flit decoder comprising: an error correction code (ECC) decoder configured to generate a first ECC decoded packet fragment based on a first packet fragment (see Figure 5, ECC decoder 120 & paragraph [0046]); an interleaver circuit configured to generate a first interleaved packet based on the first ECC decoded packet fragment (paragraph [0039], “…interleaved in a 3-way manner…”); a cyclic redundancy check (CRC) decoder configured to generate an enable signal based on a failure of a first CRC decoding operation of the first interleaved packet (see Figure 5, CRC decoder 140 & paragraph [0057]); a reliability calculator configured to generate bit stream information for identifying first to N-th error-estimated symbols among a plurality of symbols of the first packet fragment (paragraph [0072], LLR calculation); and a post decoder (Figures 5 & 8, Erasure Decoding Unit 160) configured to: in response to the enable signal, generate first to N-th index values corresponding to the first to N-th error-estimated symbols, respectively, based on the bit stream information (paragraph [0074]); generate first to M-th candidate information indicating two of the first to N-th index values, which are combined without duplication and without considering an order (paragraph [0076]); generate first to M-th erasure decoded packet fragments based on the first packet fragment and the first to M-th candidate information (paragraph [0076]); and provide a selected one of the first to M-th erasure decoded packet fragments to the interleaver circuit, wherein “N” is a natural number less than a number of the plurality of symbols, and wherein “M” is NC2 (paragraph [0076], see also flow chart in Figure 7).
Referring to claim 2, Lim discloses wherein the post decoder includes: an erasure position calculator configured to be activated based on the enable signal and to generate the first to M-th candidate information based on the bit stream information; an erasure decoder configured to generate the first to M-th erasure decoded packet fragments by performing erasure decoding operations on the first packet fragment based on the first to M-th candidate information; and a selection circuit configured to select the one of the first to M-th erasure decoded packet fragments having a minimum difference value as a post decoded packet fragment based on comparison operations of each of the first to M-th erasure decoded packet fragments and the first packet fragment, and to replace the first ECC decoded packet fragment buffered by the interleaver circuit with the post decoded packet fragment (paragraphs [0075-0076]).
Referring to claim 3, Lim discloses wherein the erasure position calculator includes: a splitter configured to generate first to N-th split values, each having a bit string type based on a one-hot encoding operation of the bit stream information; an index value generator configured to generate the first to N-th index values, each having an integer type based on a type conversion operation of the first to N-th split values; a counter configured to generate a counted value corresponding to the “N” based on a count operation of the bit stream information; and a combinator configured to generate the first to M-th candidate information by performing an NC2 combinational arithmetic operation based on the first to N-th index values and the counted value (paragraphs [0075-0076]).
Referring to claim 4, Lim discloses wherein the plurality of symbols of the first packet fragment comprise first to K-th symbols, wherein each of the first to K-th symbols includes four pulse amplitude modulation (PAM)-4 symbols (“each ECC symbol includes 4 PAM-4 symbols” Paragraph [0042]), wherein the reliability calculator is configured to: determine whether at least one of the four PAM-4 symbols corresponding to a J-th symbol among the first to K-th symbols has an unreliable voltage level (“In an embodiment, the erasure decoding includes calculating a log likelihood ratio (LLR) for each PAM-4 symbol” Paragraph [0057]); in response to determining that the at least one of the four PAM-4 symbols has the unreliable voltage level (“set to 0 when the LLR is greater than or equal to the preset threshold value” Paragraph [0079]), set a bit corresponding to the J-th symbol among bits of the bit stream information to a first bit value (selecting a symbol with a high error occurrence probability among the ECC symbols included in the flit based on the LLR); and in response to determining that none of the four PAM-4 symbols have the unreliable voltage level, set the bit corresponding to the J-th symbol among the bits of the bit stream information to a second bit value (“since the PAM-4 symbol has 2-bits corresponding to 4-levels, two LLRs may be calculated with respect to one PAM-4 symbol.” Paragraph [0073] & “a bit may be set to 1 when the LLR is less than the preset threshold” Paragraph [0079]), wherein “K” is the number of the plurality of symbols of the first packet fragment, and wherein “J” is a natural number less than or equal to “K” (“each ECC symbol includes 4 PAM-4 symbols” Paragraph [0042] & “units of symbols for every 8-bit unit that is the size of the ECC symbol” Paragraph [0082]).
Referring to claim 5, Lim discloses wherein the interleaver circuit is further configured to receive the selected one of the first to M-th erasure decoded packet fragments from the post decoder, and to generate a second interleaved packet based on the selected one instead of the first ECC decoded packet fragment, and wherein the CRC decoder is further configured to perform a second CRC decoding operation on the second interleaved packet (“the CRC decoder 140 performs the CRC decoding again after the ECC decoding is re-performed by the erasure decoding unit 160.” Paragraph [0056] & “According to an embodiment, the erasure decoder 190 performs erasure processing and ECC decoding re-performing with respect to all extractable combinations of error symbol candidates.” Paragraph [0076]).
Referring to claim 6, Lim discloses wherein the CRC decoder is further configured to generate a CRC decoded packet based on to a passage of the second CRC decoding operation, and wherein the flit decoder further includes: a packet interface circuit configured to generate a transaction layer packet (TLP) and a data link layer packet (DLP) based on the CRC decoded packet, to provide the TLP to a transaction layer, and to provide the DLP to a data link layer (paragraphs [0032] & [0054-0056]).
Referring to claim 7, Lim discloses wherein the CRC decoder is further configured to generate a request signal for re-transmission of a packet including the first packet fragment based on a failure of the second CRC decoding operation (paragraph [0056]).
Referring to claim 8, Lim discloses wherein an error correction capability of the ECC decoder corresponds to one symbol per the plurality of symbols of the first packet fragment, and wherein an error correction capability of the post decoder corresponds to two symbols, whose positions are estimated, per the plurality of symbols of the first packet fragment (paragraphs [0054] & [0075]).
Referring to claim 9, Lim discloses wherein the first packet fragment has a size of 86 bytes, and wherein the first packet fragment includes 79 TLP symbols, 2 DLP symbols, 3 CRC parity symbols, and 2 ECC parity symbols (paragraphs [0039-0040]).
Referring to claim 10, Lim discloses wherein the first packet fragment has a size of 85 bytes, and wherein the first packet fragment includes 79 TLP symbols, 2 DLP symbols, 2 CRC parity symbols, and 2 ECC parity symbols (paragraphs [0039-0040]).
Referring to claim 11, Lim discloses wherein the first packet fragment has a size of 85 bytes, and wherein the first packet fragment includes 78 TLP symbols, 2 DLP symbols, 3 CRC parity symbols, and 2 ECC parity symbols (paragraphs [0039-0040]).
Referring to claim 12, Lim discloses wherein the ECC decoder is further configured to: receive a packet including the first packet fragment, a second packet fragment, and a third packet fragment, generate a second ECC decoded packet fragment based on the second packet fragment, and generate a third ECC decoded packet fragment based on the third packet fragment, and wherein the interleaver circuit is further configured to generate the first interleaved packet based on an interleaving operation of the first ECC decoded packet fragment, the second ECC decoded packet fragment, and the third ECC decoded packet fragment (paragraphs [0039], [0046], & [0054].
Referring to claim 13, Lim discloses wherein the ECC decoder includes: a packet distributor configured to generate the first packet fragment, the second packet fragment, and the third packet fragment based on a distribution operation of the packet; a first ECC sub-decoder configured to generate the first ECC decoded packet fragment based on a first ECC decoding operation of the first packet fragment; a second ECC sub-decoder configured to generate the second ECC decoded packet fragment based on a second ECC decoding operation of the second packet fragment; and a third ECC sub-decoder configured to generate the third ECC decoded packet fragment based on a third ECC decoding operation of the third packet fragment (paragraphs [0039-0042]).
Referring to claim 14, Lim discloses wherein the flit decoder supports a flit mode of a peripheral component interconnect express (PCIe) standard, and wherein the packet complies with a format of the flit mode (paragraphs [0003] & [0036]).
Referring to communication device claims 15-17 and method claims 18-20, the claims recite similar limitations as recited in claims 1-14, therefore, are similarly rejected as anticipated by Lim.
Conclusion
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Justin R. Knapp
Primary Examiner
Art Unit 2112
/JUSTIN R KNAPP/Primary Examiner, Art Unit 2112
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