DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang 20160371019 herein Kang in view of Kang 11182289 herein Kang289.
Per claim 1, Kang discloses: a nonvolatile memory including a first and a second memory area; a controller, comprising: a first core corresponding to the first memory area; a second core corresponding to the second memory area; (fig. 2; ¶0005; a first multi-chip set which includes a first volatile memory, a first non-volatile memory, and a first core configured to control the first volatile memory and the first non-volatile memory, a second multi-chip set which includes a second volatile memory, a second non-volatile memory, and a second core configured to control the second volatile memory and the second non-volatile memory,) and a host interface layer configured to set a plurality of namespace granularity units, generate a core mapping for the plurality of namespace granularity units (storage regions) and count a number of write requests allocated to the first core and the second core for each of the plurality of namespace granularity units, (¶0013; the first core is configured to first compare a wear count of each of storage regions included in the first non-volatile memory device with a reference wear count, and transmit the first logical address of the first storage region to the controller through a first channel according to a result of the first comparison.)
Kang discloses comparing a wear count of a first region and a wear count of a second region when swapping data for wear leveling but does not specifically disclose: wherein the controller performs a global wear-leveling operation by swapping data between the first memory area and the second memory area for a target namespace granularity unit (storage regions) among the plurality of namespace granularity units, based on the number of the write requests allocated to the first core and the second core for the target namespace granularity unit
However, Kang289 discloses: wherein the controller performs a global wear-leveling operation by swapping data between the first logical block address group the first memory area and the second logical block address group of the second memory area for a target namespace granularity unit (storage regions) among the plurality of namespace granularity units, based on a difference value between the number of the write requests allocated to the first core and the number of write requests allocated to the second core for the target namespace granularity unit (col. 6 line 33; the controller 130 may update mapping information that is used to map the plurality of cores 142 and 144 to the plurality of memory devices 152 and 154 based on a difference in the wear-levels between the plurality of memory devices 152 and 154 based on write counts of the write operations performed by the plurality of cores 142 and 144, respectively, and may perform a global wear-leveling operation so that an operation is performed in response to a request from the host 102 based on the updated mapping).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Kang and Kang289’s global wear-leveling to distribute wear evenly. Kang289 improves memory durability (col. 1 lines 43-46).
Per claim 2, Kang discloses: wherein the controller updates the core mapping based on a result of the swapping (¶0177; The controller 310 may map a logical address (e.g., LA0) of a wear leveling source block (e.g., a block with a high wear-count) of the first scale-out storage device 410-1 or a storage region (e.g., 16) of the wear leveling source block onto a logical address (e.g., LA101) of a hidden destination block (e.g., a block with a low wear-count) of the second scale-out storage device 430-1 or a storage region (e.g., 36) of the hidden destination block).
Per claim 3, Kang discloses: wherein the controller allocates the write requests to cores based on the updated core mapping (¶0181-182; When the logical address LA0=GLPN0 or LA0=1LPN0 is a logical address for a program (or write) operation, as shown in CASE2, the controller 310 may write program data output from the host 200 in a first page OPage#0 or 36 of the first block Block#0 of the second provision region 22 of a third storage region, e.g., the second memory region 20, …That is, the controller 310 may program the program data in the third storage region OPage#0 or 36 of the second memory region 20 instead of the first storage region Page#0 or 16 of the first memory region 10).
Per claim 4, Kang discloses: wherein the controller includes a plurality of cores, and maintains the number of the write requests when the write requests are allocated to all of the plurality of cores, and increases the number of the write requests for a part of the plurality of cores when the write requests are allocated to the part of the plurality of cores (¶0139; the first core 411-1 may compare a wear-out count of each of blocks included in a memory cell array of at least one NAND-type flash memory device NAND managed by the first core 411-1 with a reference wear-out count in response to the first request REQ1, search a block(s) having a higher count than the reference wear-out count based on a result of the comparison, and generate a first list LIST1 according to a result of the search (S103-1). The first core 411-1 may transmit the first list LIST1 to the controller 310 (S105-1). The first list LIST1 may be stored in the volatile memory 413-1 and/or at least one NAND-type flash memory device NAND connected to the first core 411-1 according to a control of the first core 411-1; the examiner interprets the limitation as tracking writes to all cores and increasing the count to the cores targeted by a write/erase).
Per claim 5, Kang discloses: wherein data in the first memory area and data in the second memory area for another namespace granularity unit except for the target namespace granularity unit are maintained when the swapping is performed (¶0013; The second core is configured to compare a wear count of each of storage regions included in the second non-volatile memory with the reference wear count, and transmit the second logical address of the second storage region to the controller through a second channel according to a result of the second comparison…. ¶0015; The controller is configured to swap first data stored in the first storage region with second data stored in the second storage region; the examiner interprets the limitation as wear leveling by storing data in the target region).
Per claim 6, Kang discloses: wherein a difference of a number of the write requests between the first memory area and the second memory area for the target namespace granularity unit is greater than a difference of a number of the write requests between the first memory area and the second memory area for another namespace granularity unit (¶0012; the first core is configured to first compare a wear count of each of storage regions included in the first non-volatile memory with a reference wear count according to the first request, ..The second core is configured to second compare a wear count of each of storage regions included in the second non-volatile memory with the reference wear count.. and wherein a first wear count for the first storage region is larger than a second wear count for the second storage region; the examiner interprets the limitation checking the wear of the source and target namespaces).
Per claim 7, Kang discloses: wherein the target namespace granularity unit includes a plurality of logical areas, and swapping data between the first memory area and the second memory area for a target logical area except for other logical areas among the plurality of logical areas is performed (¶0013; The second core is configured to compare a wear count of each of storage regions included in the second non-volatile memory with the reference wear count, and transmit the second logical address of the second storage region to the controller through a second channel according to a result of the second comparison…. ¶0015; The controller is configured to swap first data stored in the first storage region with second data stored in the second storage region;).
Per claim 8, Kang discloses: wherein data in the first memory area and data in the second memory area for the other logical areas of the target namespace granularity unit are maintained when the swapping is performed (¶0013; The second core is configured to compare a wear count of each of storage regions included in the second non-volatile memory with the reference wear count, and transmit the second logical address of the second storage region to the controller through a second channel according to a result of the second comparison…. ¶0015; The controller is configured to swap first data stored in the first storage region with second data stored in the second storage region; the examiner notes that the other areas remaining unchanged because they aren’t targeted by the swap. In other words, they are a result of the target area being swapped into).
Per claim 9, Kang discloses: wherein a difference between a number of the write requests between the first memory area and the second memory area for the target logical area is greater than a difference of a number of the write requests between the first memory area and the second memory area for another logical area included in the target namespace granularity unit (¶0012; the first core is configured to first compare a wear count of each of storage regions included in the first non-volatile memory with a reference wear count according to the first request, ..The second core is configured to second compare a wear count of each of storage regions included in the second non-volatile memory with the reference wear count.. and wherein a first wear count for the first storage region is larger than a second wear count for the second storage region; the examiner interprets the limitation checking the wear of the source and target namespace).
Per claim 10, Kang discloses: a nonvolatile memory including a plurality of memory areas; and a controller including a plurality of cores corresponding to the plurality of memory areas, and configured to set a plurality of namespace granularity units, (fig. 2; ¶0005; a first multi-chip set which includes a first volatile memory, a first non-volatile memory, and a first core configured to control the first volatile memory and the first non-volatile memory, a second multi-chip set which includes a second volatile memory, a second non-volatile memory, and a second core configured to control the second volatile memory and the second non-volatile memory,) generate a core mapping between the plurality of cores and the plurality of namespace granularity units, count a number of write requests for each core in each of the plurality of namespace granularity units (¶0013; the first core is configured to first compare a wear count of each of storage regions included in the first non-volatile memory device with a reference wear count, and transmit the first logical address of the first storage region to the controller through a first channel according to a result of the first comparison.) and perform a global wear-leveling operation by swapping data between cores within a target namespace granularity unit among the plurality of namespace granularity units based on the number of the write requests for the cores within the target namespace granularity unit (¶0013; A first wear count of the first storage region is larger than a second wear count of the second storage region. Each of the first storage region and the second storage region is a block or a page….¶0013; The second core is configured to compare a wear count of each of storage regions included in the second non-volatile memory with the reference wear count, and transmit the second logical address of the second storage region to the controller through a second channel according to a result of the second comparison…. ¶0015; The controller is configured to swap first data stored in the first storage region with second data stored in the second storage region).
Per claim 11, Kang discloses: wherein the controller selects a first core and a second core among the cores for the global wear-leveling operation and controls the nonvolatile memory to swap first data in a first memory area corresponding to the first core and second data in a second memory area corresponding to the second core, based on the number of the write requests for the cores in the target namespace granularity unit (¶0175; the controller 310 may swap a logical address (e.g., LA0) of a wear leveling source block (e.g., a block with a high wear-count) of the first scale-out storage device 410-1 or a storage region (e.g., 16) of the wear leveling source block with a logical address (e.g., LA100) of a wear leveling destination block (e.g., a block with a low wear-count) of the second scale-out storage device 430-1 or a storage region (e.g., 26) of the wear leveling destination block. Accordingly, the data storage device 300 or 300A may perform wear leveling (i.e., global weal leveling) on the clusters 410 and 430 or the scale-out storage devices 410-1 and 430-1).
Claims 12-13 are the device claims corresponding to the device claims 2-3 and are rejected under the same reasons set forth in connection with the rejection of claims 2-3.
Per claim 14, Kang discloses: a nonvolatile memory including a first and a second memory area; a controller, comprising :a first core corresponding to the first memory area and a second core corresponding to the second memory area; (fig. 2; ¶0005; a first multi-chip set which includes a first volatile memory, a first non-volatile memory, and a first core configured to control the first volatile memory and the first non-volatile memory, a second multi-chip set which includes a second volatile memory, a second non-volatile memory, and a second core configured to control the second volatile memory and the second non-volatile memory,) and a host interface layer configured to set a plurality of namespace granularity units and manage a count of write requests allocated to each of the first core and the second core for each of the plurality of namespace granularity units, (¶0013; the first core is configured to first compare a wear count of each of storage regions included in the first non-volatile memory device with a reference wear count, and transmit the first logical address of the first storage region to the controller through a first channel according to a result of the first comparison.) wherein the controller performs a global wear-leveling operation by swapping data between the first memory area and the second memory area for a target namespace granularity unit among the plurality of namespace granularity units, based on the count of the write requests allocated to the first core and the second core for the target namespace granularity unit (¶0013; A first wear count of the first storage region is larger than a second wear count of the second storage region. Each of the first storage region and the second storage region is a block or a page….¶0013; The second core is configured to compare a wear count of each of storage regions included in the second non-volatile memory with the reference wear count, and transmit the second logical address of the second storage region to the controller through a second channel according to a result of the second comparison…. ¶0015; The controller is configured to swap first data stored in the first storage region with second data stored in the second storage region).
Per claim 15, Kang discloses: wherein the host interface layer manages the count of the write requests allocated to each of the first core and the second core for each of the plurality of namespace granularity units with a difference value of the count of the write requests between the first core and the second core for each of the plurality of namespace granularity units (¶0012; the first core is configured to first compare a wear count of each of storage regions included in the first non-volatile memory with a reference wear count according to the first request, ..The second core is configured to second compare a wear count of each of storage regions included in the second non-volatile memory with the reference wear count.. and wherein a first wear count for the first storage region is larger than a second wear count for the second storage region; the examiner interprets the limitation checking the wear of the source and target namespaces).
Claims 16-18 are the device claims corresponding to the device claims 2-3 and are rejected under the same reasons set forth in connection with the rejection of claims 2-3.
Per claim 19, Kang discloses: setting a plurality of namespace granularity units; generating a core mapping between a plurality of cores and the plurality of namespace granularity units ; (fig. 2; ¶0005; a first multi-chip set which includes a first volatile memory, a first non-volatile memory, and a first core configured to control the first volatile memory and the first non-volatile memory, a second multi-chip set which includes a second volatile memory, a second non-volatile memory, and a second core configured to control the second volatile memory and the second non-volatile memory,) counting a number of write requests for each of the plurality of cores within each of the plurality of namespace granularity units; (¶0013; the first core is configured to first compare a wear count of each of storage regions included in the first non-volatile memory device with a reference wear count, and transmit the first logical address of the first storage region to the controller through a first channel according to a result of the first comparison.) perform a global wear-leveling operation by swapping data between cores in a target namespace granularity unit among the plurality of namespace granularity units based on the number of the write requests for the cores within the target namespace granularity unit; and updating the core mapping based on a result of the swapping (¶0013; A first wear count of the first storage region is larger than a second wear count of the second storage region. Each of the first storage region and the second storage region is a block or a page….¶0013; The second core is configured to compare a wear count of each of storage regions included in the second non-volatile memory with the reference wear count, and transmit the second logical address of the second storage region to the controller through a second channel according to a result of the second comparison…. ¶0015; The controller is configured to swap first data stored in the first storage region with second data stored in the second storage region).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang and Kang289 in view of Miller et al. 20230244568 herein Miller.
Per claim 20, Kang discloses tracking the wear count for the cores in each region as disclosed supra in the rejection of claim 19 does not specifically disclose: receiving write data from an external device; dividing the write data by a set slicing size; allocating the divided write data to at least one core among the plurality of cores; and increasing the number of the write requests of the at least one core to which the divided write data is allocated.
However, Miller discloses: receiving write data from an external device; dividing the write data by a set slicing size; allocating the divided write data to at least one core among the plurality of cores; (¶0234; Portions of the dataset may be distributed across the different storage devices. For example, a dataset A is distributed into data portions A1, A2, and A3. Each portion may comprise a predetermined amount of data such as predetermined amount of kilobytes, megabytes, or some other predetermined amount. Readers will appreciate that a storage array controller 101 may therefore read a stripe 401 of data by reading the individual portions that are stored on each storage device 402, 404, 406, 408, and 410. Moreover, readers will appreciate that while a portion (or shard) of a dataset may be of a specific size, such as 512 bytes, a device (such as the storage array controller 101) may be configured to read data from the portion at other granularities (e.g., 64 bytes or 4096 bytes at a time) when reading a plurality of portions of a data strip) and increasing the number of the write requests of the at least one core to which the divided write data is allocated¶0044; the wear-count may include an erase count which represents how many times a corresponding block is erased, a program count which represents how many times a corresponding block is programmed…. Here, the erase count may be understood as a concept which includes a program-erase (P/E) cycle; the examiner notes that the combined teaching disclose a distributed data storage wherein the P/E counts is tracked across the different namespace and their respective cores.
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Kang, Kang289 and Miller’s distributed data sets into zoned namespaces for parallel processing. Miller increases throughput. Miller improves the efficiency of data placement (¶0190; With the zones aligned to the internal physical properties of the device, several inefficiencies in the placement of data can be eliminated).
Response to Arguments
Applicant’s arguments, filed 7/21/26, with respect to the rejection(s) of claim(s) 1, 14 and 19 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kang289. Kang289 discloses the controller 130 may update mapping information that is used to map the plurality of cores 142 and 144 to the plurality of memory devices 152 and 154 based on a difference in the wear-levels between the plurality of memory devices 152 and 154 based on write counts of the write operations performed by the plurality of cores 142 and 144, respectively, and may perform a global wear-leveling operation so that an operation is performed in response to a request from the host 102 based on the updated mapping.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
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