Prosecution Insights
Last updated: April 19, 2026
Application No. 19/080,540

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING SAME

Non-Final OA §102
Filed
Mar 14, 2025
Examiner
GANNON, LEVI
Art Unit
2849
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co. Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 2m
To Grant
89%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
1225 granted / 1484 resolved
+14.5% vs TC avg
Moderate +7% lift
Without
With
+6.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
29 currently pending
Career history
1513
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
40.4%
+0.4% vs TC avg
§102
36.7%
-3.3% vs TC avg
§112
14.0%
-26.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1484 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 6 is objected to because of the following informalities: Claim 6, line 4: The term “data” is misspelled “dada”. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sako et al. (US 2012/0249114; “Sako”). Regarding claim 1, Sako teaches a semiconductor device (1; Figure 1) comprising: a semiconductor element (Di) configured to output a compensation voltage (Vf) corresponding to temperature (para. [0035]); a constant current circuit (P3) configured to output a constant current (Iout) so as to compensate for temperature dependence according to a comparison (with error amp 25) of the compensation voltage (Vf) and a reference voltage (between P2 and Ri); an oscillation circuit (30; see figures 7-8) configured to output an oscillation signal (CLK) according to the constant current (Iout); a check voltage generation circuit (11) configured to output a check voltage (Vconst); and a signal generation circuit (21) configured to output (to P1) a temperature information signal (based on temperature dependent voltage Vf; para. [0035] and [0037]) corresponding to the compensation voltage (Vf) and the check voltage (Vconst). As for claim 9, Sako teaches an electronic device (microprocessor 2; figure 7) comprising: the semiconductor device (1) according to claim 1. Allowable Subject Matter Claims 2-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The best prior art reference of record, Sako, fails to teach: “wherein the check voltage generation circuit is configured to be capable of changing a voltage value of the check voltage, and the signal generation circuit generates, for the voltage value of the check voltage that has been changed, the temperature information signal according to a result of the comparison with the compensation voltage.”, as set forth in claim 2. Conclusion The prior art references made of record and not relied upon teach semiconductor devices, comprising: diodes, constant current sources, oscillation circuits, and voltage comparators. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEVI GANNON whose telephone number is (571)272-7971. The examiner can normally be reached 7:00AM-4:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LEVI GANNON/Primary Examiner, Art Unit 2849 March 5, 2026
Read full office action

Prosecution Timeline

Mar 14, 2025
Application Filed
Mar 07, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
89%
With Interview (+6.7%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 1484 resolved cases by this examiner. Grant probability derived from career allow rate.

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