Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 and 12-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Virani, US PGPub 2024/0069799.
With respect to claim 1, Virani teaches a system comprising:
a set of memory components of a memory sub-system (pars. 36-37, memory 140 is the memory sub-system, memory 140 containing memory components, such as memory cells, pages, sub-blocks, or planes);
at least one processing device operatively coupled to the set of memory components (pars. 36-37, controller 130); and
one or more shuttle buffers coupled between the set of memory components and a host (par. 62, the set of buffers), the at least one processing device configured to perform operations comprising:
receiving, from the host, a request to program a collection of data, the collection of data having a size corresponding to an individual unit size of an individual component of the set of memory components (par. 61, the write command received from the host, with a size of data the size of a transfer unit TU, which corresponds to the LBA size);
placing the collection of data in an individual shuttle buffer of the one or more shuttle buffers (par. 62, the data from the write command is placed in the set of buffers); and
storing the collection of data from the individual shuttle buffer to the individual component of the set of memory components without waiting for additional data to be received from the host (par. 68, in the case that all of the buffers are not full, instead of waiting for more data from the host, a read-modify-write operation occurs, which merges data into the buffers and writes to memory).
With respect to claim 2, Virani teaches the system of claim 1, wherein the request is received from a first application being executed by the host that is associated with a first namespace of a plurality of namespaces (par. 18, the host provides a namespace identifier along with the LBA for a memory access).
With respect to claim 3, Virani teaches the system of claim 2, wherein the first namespace is associated with a first portion of a logical address space corresponding to the set of memory components, and wherein a second namespace of the plurality of namespaces is associated with a second portion of the logical address space corresponding to the set of memory components (par. 51, the first and second namespaces).
With respect to claim 4, Virani teaches the system of claim 1, wherein the memory sub-system comprises a solid-state drive (par. 129, memory device 120 may be a solid-state drive).
With respect to claim 5, Virani teaches the system of claim 1, wherein the collection of data is programmed directly to the individual component using a single buffer comprising the individual shuttle buffer and without passing through any other buffers (par. 68, the data is merged into the one or more data buffers, without using any other buffers).
With respect to claim 6, Virani teaches the system of claim 1, the operations comprising:
determining a maximum number of regions of the set of memory components that are programmable in parallel (pars. 61-62, determining the number of TUs that correspond to a BU, which is maximum number of regions that are programmable in parallel); and
generating a quantity of shuttle buffers in the one or more shuttle buffers corresponding to the maximum number of regions of the set of memory components that are programmable in parallel (pars. 61-62, generating the set of buffers that corresponds to the number of TUs in a BU).
With respect to claim 7, Virani teaches the system of claim 1, wherein the collection of data is received from the host in a particular arrangement, and wherein the collection of data is programmed to the individual component in the same particular arrangement (pars. 616-2, the data is received in the units of a TU/LBA and programmed to the buffers in the same units).
With respect to claim 8, Virani teaches the system of claim 1, wherein the host sequentially adds portions of data associated with one or more applications to the collection of data to align the collection of data with the individual unit size of the individual component (par. 65, the data is added to the set of buffers).
With respect to claim 9, Virani teaches the system of claim 8, wherein the host transmits the request to program the collection of data in response to determining that the collection of data has the size corresponding to the individual unit size of the individual component (par. 65, data having the size of a TU is programmed to the buffer).
With respect to claim 10, Virani teaches the system of claim 1, wherein the individual unit size is greater than a 4 KB page size (par. 17, the size of a logical block might be 8 KB or 16 KB).
With respect to claim 12, Virani teaches the system of claim 10, wherein the operations comprise:
maintaining a set of large indirection units (IUs) (par. 23, the L2P table including a set of bundled units (BUs); and
associating, in the set of large IUs, an individual logical address received from the host with an individual unit of the individual component corresponding to the individual unit size that is greater than 4 KB (par. 23, associating the L2P table entries with the TUs. The TUs can be greater than 4 KB, as discussed in par. 17).
With respect to claim 13, Virani teaches the system of claim 1, wherein the one or more shuttle buffers are implemented by SRAM or DRAM (par. 62, DRAM buffers or SRAM buffers).
With respect to claim 14, Virani teaches the system of claim 1, the operations comprising:
transmitting, to the host, configuration information indicating the individual unit size of the individual component that is greater than 4 KB (par. 17, the logical block may be 8 KB or 16 KB).
With respect to claim 15, Virani teaches the system of claim 1, the operations comprising: receiving, from the host, an additional request to program a set of data; determining that the set of data is smaller than the individual unit size of the individual component; and in response to determining that the set of data is smaller than the individual unit size of the individual component, retrieving a portion of data having a size corresponding to the individual unit size of the individual component (pars. 65 and 68, depending on a size of data to be written or on a quantity of logical addresses indicated in the write command, the memory device and/or the controller may be configured to store data in multiple buffers of the set of buffers; and the memory device and/or the controller may perform a read-modify-write operation to merge in data to the one or more buffers and then write data stored by all of the buffers to the memory).
With respect to claim 16, Virani teaches the system of claim 15, the operations comprising: modifying the retrieved portion of data using the set of data to generate a new portion of data having the set of data and being of the size corresponding to the individual unit size; and storing the new portion of data to the individual component (pars. 65 and 68, depending on a size of data to be written or on a quantity of logical addresses indicated in the write command, the memory device and/or the controller may be configured to store data in multiple buffers of the set of buffers; and the memory device and/or the controller may perform a read-modify-write operation to merge in data to the one or more buffers and then write data stored by all of the buffers to the memory).
With respect to claim 17, Virani teaches the system of claim 1, the operations comprising: transmitting a confirmation of storage to the host in response to successfully programming the collection of data to the individual component (par. 30, the controller communicates with the host while instructing memory operations to be performed).
Claims 18-19 are a method that corresponds to claims 1-2, and are rejected using similar logic.
Claim 20 is a computer-readable storage medium that corresponds to claim 1, and is rejected using similar logic.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Virani, as applied to claims 1 and 10 above, in view of Yano, et al., US PGPub 2011/0307667.
With respect to claim 11, Virani teaches all limitations of the parent claim, but fails to specifically disclose the individual unit size is 512 KB. Yano further teaches the system of claim 10, wherein the individual unit size comprises 512 KB (par. 54, a logical block is 512 KB).
It would have been obvious to one of ordinary skill in the art, having the teachings of Virani and Yano before him before the earliest effective filing date, to modify the SSD of Virani with the SSD of Yano, as a logical block size of 512 KB would be obvious to try. Virani teaches that a logical block may be 512 bytes, 4096 bytes (4 kilobytes (KB)), 8192 bytes (8 KB), or 16384 bytes (16 KB), among other examples, depending on a configuration of the memory device, as disclosed in par. 17. Yano discloses that a common logical block size for an SSD is 512 KB. Given that there are a finite number of sizes used for a logical block size for an SSD, it would be obvious to try the 512 KB size of Yano, since you are choosing from finite number of identified, predictable solutions, with a reasonable expectation of success. See MPEP § 2143 I (E).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ryan et al., US PGPub 2016/0350010, teaches receiving a small amount of data, reading a full block from memory and combining the small amount of data with the read data in a temporary buffer for writing to memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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