DETAILED ACTION
Notice of Pre-AIA or AIA Status
1.The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
2. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) -706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-l.jsp.
3. Claims 15-17,21-23 and 28-30 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1,3-7,9-13,15-18 of U.S. Patent No 12,255,994. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the current application encompass the same subject matter as the patent claims, but with obvious wording variations such as securing operations accessing a non-volatile storage area of a memory device. The method comprising generating, by firmware of a memory device, a cryptographic key using a value of a physically unclonable function (PUF); writing, by the firmware, the cryptographic key to a volatile storage area; receiving, by the firmware, a command accessing a non-volatile storage area from a host processor; and processing, by the firmware, the command using the cryptographic key;
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi 759 F.2d at 896, 225 USPQat651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). " ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 15-17, 20-23, 26-30 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Shacham (US Pub.No.2014/0310536) in view of Martel (US Pat.No.11,455,432).
6. Regarding claim 15 Shacham teaches a method comprising: receiving, at a memory device, an insecure input/output (I/O) command from a host processor (Figs.2,4 and Para:0038, Para:0047 teaches an application processing circuit 202 sends a write command 208 to the host storage controller 204 identifying data to be written to the storage device 206, which the controller sends a write command request to the storage device . Para:0041 and Para:0056 teaches receiving a read command from the requesting host software and issuing a read command to the storage device, i.e., an application processing circuit executing host software and a host storage controller that receives read and write commands originating from the host software. The host storage controller responds by issuing corresponding storage commands to an external storage device. The command received from the host before the inline cryptographic processing, which is interpreted as insecure I/O command because the command and associated data have not yet undergone the cryptographic processing that secures the storage transaction);
converting the insecure I/O command into a secure I/O command (Para:0038, Para:0040 and Para:0047-0049 teaches the host storage controller receives a host write command, obtains encryption key, encrypts the associated data, and sends the encrypted data to the storage device. Para:0041 and Para:0056-0057 teaches the host storage controller receives a host read command, retrieves encrypted data, obtains a decryption key, decrypts the encrypted data, and provides the decrypted data to the requesting host software. i.e., converting the host read or write request into a storage transaction in which the associated data are cryptographically processed);
by loading a cryptographic key from a volatile storage area (Fig.3, Para:0044, Para:0048 and Para:0057 teaches the internal shared storage 332 include SRAM, DDR,SDRAM or DRAM and key/parameter storage element 333 stores encryption keys. The host storage controller obtains an initial key from host memory for use in encrypting or decrypting the data);
and modifying data associated with the insecure I/O command using the cryptographic key (Para:0040-0041, Para:0048-0049 and Para:0056-0057 teaches modifying data associated with the host command using cryptographic key by encrypting write data or decrypting the read data);
and executing the secure I/O command storage to access a non-volatile storage area (Para:0040-0041, Para:0045, Para:0049 and Para:0056-0057 teaches executing the secure storage operation to access non-volatile storage by sending encrypted data to the storage device or retrieving encrypted data from the storage device. The storage device may be an SD card, eMMC device or UFS device).
Shacham teaches all the above claimed limitations but does not expressly teach performing all the claimed operations using an NVM controller integrated with the memory device and supplied with an encryption key.
Martel teaches an NVM controller, volatile memory and non-volatile memory (Figs.1,2, Col.1, lines.45-59 and Col.2, lines.10-25 teaches a first processor executing a host operating system, a secure enclave processor, and a non-volatile memory controller to access encrypted data within a non-volatile memory using a volume encryption key. Col.5, lines.59-66 teaches the memory 150, include SRAM or DRAM, and NVM 105, which include NAND flash or NOR flash);
and executing the secure command to access a non-volatile storage area of the memory device (Col.4, lines.5-17 and Col.18, lines.15-33 teaches a cryptographic engine in the NVM controller uses a volume encryption key to automatically decrypt data read from the NVM and encrypt the data written to NVM).
It would have been obvious to one of ordinary skill in the art at the time before the effective filling date of the claimed invention to implement Shacham’s inline encryption and decryption operations in Martel’s NVM controller. The combination would allow host read and write command to be secured automatically and transparently when accessing non-volatile memory, without requiring the host software to perform the cryptographic operations.
7. Regarding claim 16 Shacham in view of Martel teaches the method of claim 15, wherein the insecure I/O command comprises a read command, and wherein converting the insecure I/O command to a secure I/O command comprises: reading encrypted data from the non-volatile storage area (Shacham: Fig.9, Para:0041 and Para:0056-0057 teaches receiving a read command from requesting host software and sending a corresponding read command to an off-chip storage device. The controller receives encrypted data from the storage device and obtains a decryption key using an initial key stored in host memory); decrypting the encrypted data using the cryptographic key to generate decrypted data; and returning the decrypted data to the host processor (Shacham: Para:0057 teaches decrypting the encrypted data and returning the decrypted data to the requesting host software by writing the decrypted data to host memory.
Martel: Col.18, lines.15-33 teaches cryptographic engine in NVM controller uses a volume encryption key to automatically decrypt data read from NVM)
8. Regarding claim 17 Shacham in view of Martel teaches the method of claim 15, wherein the insecure I/O command comprises a write command, and wherein converting the insecure I/O command to a secure I/O command comprises: extracting data from the write command (Shacham:Para:0038, Para:0040 and Para:0047-0049 teaches receiving a write command from host software that identifies data to be stored. The host storage controller obtains the data from host memory, obtains the encryption key and encrypt the data); encrypting the data using the cryptographic key to generate encrypted data; and writing the encrypted data to the non-volatile storage area (Para:0040, Para:0049, Para:0073 and Para:0075 teaches sending the encrypted data to the storage device for storage at identified location. Martel: Col.18, lines.25-30 teaches automatically encrypting data written to a file system in NVM).
9. Regarding claim 20 Shacham in view of Martel teaches the method of claim 15, wherein the cryptographic key comprises a symmetric key, and wherein modifying data associated with the insecure I/O command comprises using one of: Advanced Encryption Standard (AES), Salsa20/ChaCha20, CAST, Twofish, IDEA, Serpent, RC5, RC6, Camellia, or ARIA algorithms (Shacham:Para:0048-0049 teaches using an initial vector and an initial key with an AES encryption function to encrypt the data.
Martel: Col.9, lines.14-18, lines.37-43; Col.10, lines.16-28 teaches AES encryption engines and cryptographic processing using AES)
10. Regarding claim 21 Shacham teaches a memory device comprising: a non-volatile storage area; a volatile storage area; and a controller configured to: receive an insecure input/output (I/O) command from a host processor, convert the insecure I/O command to a secure I/O command by loading a cryptographic key from the volatile storage area and modifying data associated with the insecure I/O command using the cryptographic key, and execute the secure I/O command to access the non-volatile storage area (see, the rejection for claim 15).
11. Regarding claim 22 Shacham in view of Martel teaches the memory device of claim 21, wherein the insecure I/O command comprises a read command, and wherein the controller is configured to convert the insecure I/O command to the secure I/O command by: reading encrypted data from the non-volatile storage area; decrypting the encrypted data using the cryptographic key to generate decrypted data; and returning the decrypted data to the host processor (see, the rejection for claim 16).
12. Regarding claim 23 Shacham in view of Martel teaches the memory device of claim 21, wherein the insecure I/O command comprises a write command, and wherein the controller is configured to convert the insecure I/O command to the secure I/O command by: extracting data from the write command; encrypting the data using the cryptographic key to generate encrypted data; and writing the encrypted data to the non-volatile storage area (see, the rejection for claim 17).
13. Regarding claim 26 Shacham in view of Martel teaches the memory device of claim 21, wherein the memory device comprises at least one of: a solid-state drive (SSD), an embedded multimedia card (eMMC), a Universal Flash Storage (UFS) drive, a universal serial bus (USB) flash drive, or a secure digital (SD) card (Shacham: Para:0045, Para:0047 and Para:0056 teaches a permanent or semi-permanent storage including a Secure Digital (SD) card, an embedded multimedia card (e.MMC or e-MMC) device, and UFS device).
14. Regarding claim 27 Shacham in view of Martel teaches the memory device of claim 21, wherein the non-volatile storage area comprises at least one of: NAND flash memory, 3D cross-point memory, phase-change memory (PCM), ferroelectric random-access memory (FeRAM), or resistive random access memory (RRAM) (Martel: Col.5, lines.59-66 teaches NVM 105 include flash memory, including NAND flash memory or NOR flash memory).
15. Regarding claim 28 Shacham a non-transitory computer-readable storage medium storing computer program instructions that, when executed by a controller of a memory device, cause the controller to perform operations comprising: receiving an insecure input/output (I/O) command from a host processor; converting the insecure I/O command to a secure I/O command by: loading a cryptographic key from a volatile storage area of the memory device, and modifying data associated with the insecure I/O command using the cryptographic key; and executing the secure I/O command to access a non-volatile storage area of the memory device (see, the rejection for claim 15).
16. Regarding claim 29 Shacham in view of Martel teaches non-transitory computer-readable storage medium of claim 28, wherein the insecure I/O command comprises a read command, and wherein converting the insecure I/O command to the secure I/O command comprises: reading encrypted data from the non-volatile storage area; decrypting the encrypted data using the cryptographic key to generate decrypted data; and returning the decrypted data to the host processor (see, the rejection for claim 16).
17. Regarding claim 30 Shacham in view of Martel teaches the non-transitory computer-readable storage medium of claim 28, wherein the insecure I/O command comprises a write command, and wherein converting the insecure I/O command to the secure I/O command comprises: extracting data from the write command; encrypting the data using the cryptographic key to generate encrypted data; and writing the encrypted data to the non-volatile storage area (see, the rejection for claim 17).
18. Regarding claim 33 Shacham in view of Martel teaches the non-transitory computer-readable storage medium of claim 28, wherein the cryptographic key comprises a symmetric key, and wherein modifying data associated with the insecure I/O command comprises using one of: Advanced Encryption Standard (AES), Salsa20/ChaCha20, CAST, Twofish, IDEA, Serpent, RC5, RC6, Camellia, or ARIA algorithms (see, the rejection for claim 20).
19. Claim(s) 18, 24 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Shacham (US Pub.No.2014/0310536) in view of Martel (US Pat.No.11,455,432) as applied to claims 15, 21 and 28 above and in view of Biesecker (US Pat.No.10,169,563) and further in view of Van Der Sluis (US Pub.No.9,430,406)
20. Regarding claim 18 Shacham, in view of Martel teaches all the above claimed limitations, but fails to teach the method of claim 15, wherein loading the cryptographic key from the volatile storage area comprises: determining if the cryptographic key is present in the volatile storage area; and in response to determining the cryptographic key is not present, regenerating the
cryptographic key using a value from a physically unclonable function (PUF).
Biesecker teaches determining if the cryptographic key is present in the volatile storage area; and in response to determining the cryptographic key is not present, regenerating the
cryptographic key (Fig.3 and Col.9, lines.21-47; Col.10, lines.23-39 teaches checking whether volatile memory containing an encryption key has been cleared or corrupted. If the key remains present, the replacement process ends, if the key has been cleared, the process obtains the key again).
It would have been obvious to one of ordinary skill in the art at the time before the effective filling date of the claimed invention to modify the teaching, taught by Shacham in view of Martel to include, determining whether if the cryptographic key is present in the volatile storage, as taught by Biesecker, this check will allow the system to begin key restoration when the key has been cleared and to avoid that process when the key remains present.
Shacham, in view of Martel and in view of Biesecker, teaches all the above claimed limitations but fails to teach regenerating the missing key using a PUF value.
Van Der Sluis teaches regenerating the missing key using a PUF value (Col.1, lines.2-21; Col. 6, lines.40-67 teaches deriving a reproducible cryptographic key from the power up contents of a volatile memory PUF. Derving the key again after the key has been deleted).
It would have been obvious to one of ordinary skill in the art at the time before the effective filling date of the claimed invention to modify the teaching, taught by Shacham in view of Martel and in view of Biesecker to include regenerating the missing key using a PUF value, as taught by Van Der Sluis, this would allow the system to regenerate the key locally after loss of volatile memory contents and reduces the risk of extracting a key from permanent key storage.
21. Regarding claim 24 Shacham in view of Martel teaches the memory device of claim 21, further comprising a physically unclonable function (PUF), and wherein the controller is configured to load the cryptographic key by: determining if the cryptographic key is present in the volatile storage area; and in response to determining that the cryptographic key is not present, regenerating the cryptographic key using a value from the PUF (see, the rejection for claim 18).
22. Regarding claim 31 Shacham in view of Martel teaches the non-transitory computer-readable storage medium of claim 28, wherein loading the cryptographic key from the volatile storage area comprises: determining if the cryptographic key is present in the volatile storage area; and in response to determining that the cryptographic key is not present, regenerating the cryptographic key using a value from a physically unclonable function (PUF) of the memory device (see, the rejection for claim 18).
23. Claim(s) 19, 25 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Shacham (US Pub.No.2014/0310536) in view of Martel (US Pat.No.11,455,432) as applied to claims 15, 21 and 28 above and further in view of Ducharme (US Pub.No.7,165,180).
24. Regarding claim 19 Shacham teaches storing encryption keys in internal storage that may include SRAM or DRAM (Para:0044). Martel teaches a cryptographic engine in NVM controller (Col.4, lines.5-17) but fails to teach reading the cryptographic key from a preconfigured location in the volatile storage area that is hardwired to a controller of the memory device.
Ducharme teaches reading the cryptographic key from a preconfigured location in the volatile storage area that is hardwired to a controller of the memory device (Col.4, lines.43-55 and Col.5, lines.4-30 teaches a key register that may use volatile RAM and may be physically connected only to an encryption engine. Accessing a key register at a specified memory address).
It would have been obvious to one of ordinary skill in the art at the time before the effective filling date of the claimed invention to modify the teaching, taught by Shacham in view of Martel to include reading the cryptographic key from a preconfigured location in the volatile storage area that is hardwired to a controller of the memory device, as taught by Ducharme, such a setup would restrict external access to the key.
25. Regarding claim 25 Shacham teaches storing encryption keys in internal storage that may include SRAM or DRAM (Para:0044). Martel teaches a cryptographic engine in NVM controller (Col.4, lines.5-17) but fails to teach the memory device of claim 21, wherein the controller is hardwired to a preconfigured location in the volatile storage area at which the cryptographic key is stored, and wherein the controller is configured to load the cryptographic key by reading the cryptographic key from the preconfigured location.
Ducharme teaches the controller is hardwired to a preconfigured location in the volatile storage area at which the cryptographic key is stored, and wherein the controller is configured to load the cryptographic key by reading the cryptographic key from the preconfigured location (Col.4, lines.43-55 and Col.5, lines.4-30 teaches a key register that may use volatile RAM and whose output may be physically connected only to an encryption engine. Accessing a key register at a specified memory address) .
It would have been obvious to one of ordinary skill in the art at the time before the effective filling date of the claimed invention to modify the teaching, taught by Shacham in view of Martel to include the controller is hardwired to a preconfigured location in the volatile storage area at which the cryptographic key is stored, and wherein the controller is configured to load the cryptographic key by reading the cryptographic key from the preconfigured location, as taught by Ducharme, such a setup would restrict external access to the key.
26. Regarding claim 32 Shacham teaches storing encryption keys in internal storage that may include SRAM or DRAM (Para:0044). Martel teaches a cryptographic engine in NVM controller (Col.4, lines.5-17) but fails to teach the non-transitory computer-readable storage medium of claim 28, wherein loading the cryptographic key comprises reading the cryptographic key from a preconfigured location in the volatile storage area that is hardwired to the controller.
Ducharme teaches reading the cryptographic key from a preconfigured location in the volatile storage area that is hardwired to the controller (Col.4, lines.43-55 and Col.5, lines.4-30 teaches a key register that may use volatile RAM and may be physically connected only to an encryption engine. Accessing a key register at a specified memory address) .
It would have been obvious to one of ordinary skill in the art at the time before the effective filling date of the claimed invention to modify the teaching, taught by Shacham in view of Martel to include reading the cryptographic key from a preconfigured location in the volatile storage area that is hardwired to a controller of the memory device, as taught by Ducharme, such a setup would restrict external access to the key.
27. Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Shacham (US Pub.No.2014/0310536) in view of Martel (US Pat.No.11,455,432) as applied to claim 28 above and further in view of Camp (US Pub.No.9,612,978).
28. Regarding claim 34 Shacham in view of Martel teaches all the above claimed limitations, but fails to teach the non-transitory computer-readable storage medium of claim 28, the operations further comprising, in response to receiving an interrupt event indicating a power-off condition at the memory device, erasing the cryptographic key from the volatile storage area, wherein encrypted data stored in the non-volatile storage area remains stored without corresponding storage of the cryptographic key after the power-off condition.
Camp teaches in response to receiving an interrupt event indicating a power-off condition at the memory device, erasing the cryptographic key from the volatile storage area, wherein encrypted data stored in the non-volatile storage area remains stored without corresponding storage of the cryptographic key after the power-off condition (Col.11, lines.1-15; Col.17, lines.1-10 teaches a flash storage system that stores encrypted data in a flash memory array and stores a user key in volatile controller memory. An emergency shutoff signal informs the CPU of a power off condition. The CPU then immediately shuts down the system, causing the key to be cleared from volatile memory. Figs. 7A, 8A and Col.17, lines.15-35; Col.20, lines.30-50 teaches the encrypted data remains in the flash memory array).
It would have been obvious to one of ordinary skill in the art at the time before the effective filling date of the claimed invention to modify the teaching, taught by Shacham in view of Martel to include, in response to receiving an interrupt event indicating a power-off condition at the memory device, erasing the cryptographic key from the volatile storage area, wherein encrypted data stored in the non-volatile storage area remains stored without corresponding storage of the cryptographic key after the power-off condition, as taught by Camp, the combined teaching would yield a predictable result of preventing access to encrypted data after shutdown without erasing the data stored in the non-volatile memory.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREENA T CATTUNGAL whose telephone number is (571)270-0506. The examiner can normally be reached Mon-Fri : 7:30 AM-5 PM EST.
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/DEREENA T CATTUNGAL/Primary Examiner, Art Unit 2431
