DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 5, 2025 has been considered by the examiner. An initialed copy of the IDS is included with this Office Action.
Drawings
The drawings filed on March 14, 2025 are acceptable.
Specification
The disclosure is objected to because of the following informalities:
in paragraph [0029], it appears that “OTX1 114” on line 4 should be “OTX2 124”; the two occurrences of “ORX2 122” on line 5 should be “ORX1 112” and the two occurrences of “DSP2 120” should be “DSP1 110” since the second link 115 transmits the signal (see “received from the second link” in paragraph [0029], lines 2-3) and the first DSP 110 performs the bit error rate test (see paragraph [0029], line 1); and
similarly, in paragraph, [0030], it appears that “OTX1 114 to ORX2 122” on lines 3-4 should be “OTX2 124 to ORX1 112”.
Appropriate clarification/correction is required.
Claim Objections
The claims are objected to because of the following informalities:
in claim 7, line 1, “receive first” should be “receive a first”;
in claim 7, line 3, “receive second” should be “receive a second”;
in claim 8, line 1, the comma after “training” should be deleted;
in claim 8, line 4 “(DSP)” should be inserted after “processor”;
in claim 10, line 2, “a transmitter” should be “the first optical transmitter” (see claim 8, line 2);
in claim 10, line 3, “based on the one or more signal parameters” should be “using the one or more FEC padding bits or reserved bits” (see paragraph [0032]; and claims 4 and 17);
in claim 11, lines 2-3, “based on the one or more signal parameters” should be “using the one or more FEC padding bits or reserved bits” (see paragraph [0032]; and claims 5 and 18);
in claim 12, lines 2-3, “using the one or more signal parameters” should be “using the one or more FEC padding bits or reserved bits” (see paragraph [0032]);
in claim 13, line 2, “a” should be inserted before “first trans-impedance”;
in claim 14, line 2, “a” should be inserted before “second trans-impedance”;
in claim 15, line 1, the comma after “device” should be deleted;
in claim 17, line 2, “a transmitter” should be “the first optical transmitter” (see claim 15, line 3); and
in claim 20, line 2, “a” should be inserted before “first trans-impedance.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regard to claim 2, it is unclear what constitutes a “mirrored link” within the scope of the claim. It is unclear if all the components must be the same vendor (see paragraph [0019]), have the same functionality, and/or have the same configuration in order to constitute “mirrored link” within the scope of the claim.
With regard to claim 4, it is unclear how “a transmitter” and “a digital pre-distortion (DPD) engine” relate to the “first link” in claim 1, lines 2-3. For example, are these elements part of the “first link”? It appears that “a transmitter” on line 2 should be “the first optical transmitter” (see claim 1, line 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over (US Patent No. 2024/0048235 A1) in view of Kosugi (US Publication No. 2022/0416899 A1).
With regard to claim 1, Gareau et al. discloses the claimed invention including a system comprising:
a first link (e.g. modem 20B in FIG. 1 and see paragraph [0035] wherein the modem can include optical transceivers); and
a second link (e.g. modem 20A in FIG. 1 and see paragraph [0035] wherein the modem can include optical transceivers), wherein the second link is coupled to the first link using an active optical cable (see paragraphs [0002] and [0035])
wherein the second link is operable to communicate with the first link using one or more FEC padding bits or one or more reserved bits (see “padding/reserved sections” in paragraph [0039] and “reserved symbols or padding symbols for the messaging channel” in paragraph [0043] wherein the symbols represent bits). Gareau et al. does not explicitly disclose that the modem/optical transceiver comprises a digital signal processor, an optical transmitter and an optical receiver. FIG. 1 of Kosugi discloses an optical transceiver (100) that comprises a digital signal processor (10), an optical transmitter (20) and an optical receiver (30). Since the modems in Gareau et al. include digital signal processing (see paragraph [0037]) and the modems include (see “transmitters/receivers” in paragraph [0035]), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the “modem”/”optical transceiver” in Gareau et al. with the optical transceiver of Kosugi to obtain predictable results wherein the DSPs of the respective modems communicate using one or more FEC padding bits or one or more reserved bits as recited.
With regard to claim 2, Gareau et al. in view of Kosugi disclose the claimed invention including the second link is a “mirrored link” of the first link wherein “mirrored link” is interpreted as components from the same vendor (see paragraph [0019]). (See Gareau et al., paragraph [0051])
With regard to claim 4, Gareau et al. in view of Kosugi disclose the claimed invention including the first DSP is operable to calibrate one or more of a transmitter using the one or more FEC padding bits or reserved bits. (See Gareau et al., paragraphs [0050] and [0055] wherein the messaging channel can include “loop optimization for settings like transmitter pre-compensation and spectral shaping” read on “to calibrate one or more of a transmitter.”)
With regard to claim 5, Gareau et al. in view of Kosugi disclose the claimed invention including the first DSP is operable to perform a bit error rate test using the one or more FEC padding bits or the one or more reserved bits received from the second link. (See Gareau et al. paragraphs [0092]-[0093]) Gareau et al. discloses that “patterns” are inserted in the PAD or RES area (see paragraph [0092]) wherein the threshold of matching the pattern in the receiver is “based on the bit error rate” (see paragraph [0093]). Therefore, it is implicit that the receiver of the “patterns” inserted in the PAD or RES area performs a bit error test on the “patterns” in the PAD or RES area of the received signal in order to determine whether the threshold has been exceeded.
With regard to claim 6, Gareau et al. in view of Kosugi disclose the claimed invention including the first DSP is operable to perform time synchronization using the one or more FEC padding bits or the one or more reserved bits received from the second link. (See Gareau et al., paragraph [0092] wherein “patterns” are inserted in the PAD or RES area for timestamp point of reference and the “timestamp” is used for time synchronization)
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Gareau et al. in view of Kosugi as applied to claim 1 above, and further in view of Movassaghi et al. (US Patent No. 8,768,166 B2) and Geyer et al. (US Patent No. 11,239,919 B2). Gareau et al. in view of Kosugi disclose the claimed invention except for adjusting a first power level of the first optical transmitter based on the second power level of the second optical receiver by using the one or more FEC padding bits or the one or more reserved bits. Movassaghi et al. teaches adjusting the power level of a transmitter in a transceiver based on indication about the power level of a receiver at a partner transceiver. (See FIG. 2 and column 2, lines 59-63) Since Geyer et al. discloses transmitting information to optimize the parameters/setting of a transmitter in unused overhead (see “optimization of parameters and settings of an optical coherent transceiver through information sent over side channel” in paragraph [0014] and “possible to use unused overhead to incorporate information for side channel communications” in paragraph [0016]), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Movassaghi et al. and Geyer et al. to Gareau et al. in view of Kosugi by transmitting the indication of a receiver power level using the padding symbols or reserved symbols (i.e. “unused overhead”) in order to have an adaptable communication system for optimizing communication.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Gareau et al. in view of Kosugi as applied to claim 1 above, and further in view of Zhang (US Patent No. 12,250,101 B1). Gareau et al. in view of Kosugi disclose the claimed invention except for the first DSP receiving a first trans-impedance amplifier (TIA) output and the second DSP receiving a second trans-impedance amplifier (TIA) output. FIG. 3 of Zhang discloses a transceiver with a trans-impedance amplifier (TIA) (see 142) that provides an output to a “DSP” (wherein 144 and 126 form a “DSP”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a trans-impedance amplifier (TIA) to the receiver in the respective modems (i.e. transceivers) in Gareau et al. in view of Kosugi in order to ensure that the received signal has sufficient voltage/amplitude for subsequent processing.
Claims 8-12 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Movassaghi et al. in view of Gareau et al.
With regard to claim 8, Movassaghi et al. discloses the claimed invention including sending a first signal from a first optical transmitter coupled to a first DSP (see FIGs. 1 and 2; and “transmitted from a second optical transceiver device” in operation 202 of FIG. 4); computing, at the second DSP (see “first optical transceiver device” in operation 204 of FIG. 4), one or signal parameters of the first signal (see “receive power of the optical signals” in operation 204 of FIG. 4); generating, at the second DSP, a signal including the one or more signal parameters (see “disparity of the receive power with respect to a target receive power level” in operation 206 in FIG. 4) and sending the second signal to a first optical receiver coupled to the first DSP (see “communicate to the second optical transceiver” in operation 206 of FIG. 4) wherein FIG. 2 shows each of the first and second optical transceivers as having a transmitter (110), a DSP (e.g. 130, 150 and/or 170) and a receiver (120). However, Movassaghi et al. does not disclose that including the “one or more signal parameters” in one or more FEC padding bits or one or more reserved bits for communication to the second DSP.
Gareau et al. discloses an optical transceiver that transmits a DSP frame using padding symbols or reserved symbols for the messaging channel. (See paragraphs [0008], [0039], [0042]-[0044] and [0050]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Movassaghi et al. with the teachings of Gareau et al. by implementing the digital signal processing frame of Gareau et al. as part of TX chain circuitry 130 in the transceivers of Movassaghi et al. This combination of prior art elements yield predictable results since the teachings of Gareau et al. in the TX chain circuitry does not affect the adaptive power control techniques of Movassaghi et al. (See Movassaghi et al., column 3, lines 37-42) Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention using the FEC padding bits or reserved bits in the method/apparatus of Movassaghi et al. in view of Gareau et al. to transmit the signal parameters in order to efficiently transmit the signal parameters to the corresponding transceiver without transmitting a separate modulated signal in operation 206 of Movassaghi et al.
With regard to claim 9, Movassaghi et al. in view of Gareau et al. disclose the claimed invention including adjusting the first optical transmitter power based on the one or more signal parameters. (See Movassaghi et al., column 4, lines 32-65)
With regard to claim 10, Movassaghi et al. in view of Gareau et al. disclose the claimed invention including calibrating, at the first DSP, one or more of a transmitter based on the one or more signal parameters. (See Movassaghi et al., column 4, lines 51-58 wherein “TX bias circuitry 140” is controlled/calibrated)
With regard to claim 11, Movassaghi et al. in view of Gareau et al. disclose the claimed invention including performing, at the first DSP, a bit error test using one or more FEC padding bits or reserved bits. Gareau et al. discloses that “patterns” are inserted in the PAD or RES area (see paragraph [0092]) wherein the threshold of matching the pattern in the receiver is “based on the bit error rate” (see paragraph [0093]). Therefore, it is implicit that the receiver of the “patterns” inserted in the PAD or RES area performs a bit error test on the “patterns” in the PAD or RES area of the received signal in order to determine whether the threshold has been exceeded. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to also provide timing information via the timestamp using padding bits or reserved bits as taught by as Gareau et al. in order to further optimize the communication method/system of Movassaghi et al. in view of Gareau et al.
With regard to claim 12, Movassaghi et al. in view of Gareau et al. disclose the claimed invention including synchronizing the two DSPs (i.e. the two transceivers”) using one or more FEC padding bits or reserved bits. Gareau et al. discloses inserting “patterns” in the PAD or RES area for timestamp point of reference (see paragraph [0092]) wherein the “timestamp” is used for synchronization. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to also provide timing information via the timestamp using padding bits or reserved bits as taught by as Gareau et al. in order to further optimize the communication method/system of Movassaghi et al. in view of Gareau et al.
With regard to claim 15, Movassaghi et al. discloses the claimed invention including a first digital signal processor (see “optical transceiver module” in FIG. 1 and “second optical transceiver device” in FIG. 4) operable: to send, from a first optical transmitter coupled to the first DSP (see FIG. 2), a first signal to a second optical receiver coupled to a second digital signal processor (see operation 202 and “first optical receiver” in FIG. 4 and “optical transceiver module” in FIGs. 1 and 2); receive a second signal including signal parameters of the first signal (see operation 206 in FIG. 4); compute additional parameters of a third signal based on the one or more signal parameters of the first signal (see column 6, lines 13-16 wherein it is implicit that the repeat of operation 202 involves adjusting the power level of the transmitted signal to adjust the receive power at the first optical transceiver device); and send the third signal for transmission to the second optical receiver coupled to the second DSP (see “wherein operations 202, 204 and 206 are repeated” in column 6,lines 13-16 whereby a “third signal” is transmitted in the next iteration of the operation 202). However, Movassaghi et al. does not teach that the second signal comprises one or more FEC padding bits or one or more reserved bits wherein one or more FEC padding bits or one or more reserved bits include one or more parameters of the first signal.
Gareau et al. discloses an optical transceiver that transmits a DSP frame using padding symbols or reserved symbols for the messaging channel. (See paragraphs [0008], [0039], [0042]-[0044] and [0050]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Movassaghi et al. with the teachings of Gareau et al. by implementing the digital signal processing frame of Gareau et al. as part of TX chain circuitry 130 in the transceivers of Movassaghi et al. This combination of prior art elements yield predictable results since the teachings of Gareau et al. in the TX chain circuitry does not affect the adaptive power control techniques of Movassaghi et al. (See Movassaghi et al., column 3, lines 37-42) Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention using the FEC padding bits or reserved bits of the messaging channel in the method/apparatus of Movassaghi et al. in view of Gareau et al. to transmit the signal parameters in order to efficiently transmit the signal parameters to the corresponding transceiver without transmitting a separate modulated signal in operation 206 of Movassaghi et al.
With regard to claim 16, Movassaghi et al. in view of Gareau et al. disclose the claimed invention including the first digital signal processor is operable to adjust a power level of the third signal based on the one or more signal parameters of the first signal. (See Movassaghi et al., column 4, lines 32-65)
With regard to claim 17, Movassaghi et al. in view of Gareau et al. disclose the claimed invention including the first digital signal processor is operable to calibrate one or more of a transmitter or a digital pre-distortion engine using the one or more FEC padding bits or the one or more reserved bit. Gareau et al. teaches that the messaging channel can include “loop optimization for settings like transmitter pre-compensation and spectral shaping” read on “to calibrate one or more of a transmitter.” (See paragraphs [0050] and [0055]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed to also include additional settings/parameters in the one or more FEC padding bits or the one or more reserved provide timing information for transmitter pre-compensation and spectral shaping in order to further optimize the communication method/system of Movassaghi et al. in view of Gareau et al.
With regard to claim 18, Movassaghi et al. in view of Gareau et al. disclose the claimed invention including the first DSP is operable to perform a bit error test using one or more FEC padding bits or reserved bits. Gareau et al. discloses that “patterns” are inserted in the PAD or RES area (see paragraph [0092]) wherein the threshold of matching the pattern in the receiver is “based on the bit error rate” (see paragraph [0093]). Therefore, it is implicit that the receiver of the “patterns” inserted in the PAD or RES area performs a bit error test on the “patterns” in the PAD or RES area of the received signal in order to determine whether the threshold has been exceeded. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to also provide timing information via the timestamp using padding bits or reserved bits as taught by as Gareau et al. in order to further optimize the communication method/system of Movassaghi et al. in view of Gareau et al.
With regard to claim 19, Movassaghi et al. in view of Gareau et al. disclose the claimed invention including the first DSP is operable to perform time synchronization using one or more FEC padding bits or reserved bits. Gareau et al. discloses inserting “patterns” in the PAD or RES area for timestamp point of reference (see paragraph [0092]) wherein the “timestamp” is used for synchronization. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to also provide timing information via the timestamp using padding bits or reserved bits as taught by as Gareau et al. in order to further optimize the communication method/system of Movassaghi et al. in view of Gareau et al.
Claims 13, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Movassaghi et al. in view of Gareau et al. as applied to claims 8 and 15, respectively, above, and further in view of Zhang.
With regard to claim 13, Movassaghi et al. in view of Gareau et al. disclose the claimed invention except for receiving, at the first DSP, a first trans-impedance amplifier (TIA) output from a first (TIA). FIG. 3 of Zhang discloses a transceiver with a trans-impedance amplifier (TIA) (see 142) that provides an output to a “DSP” (wherein 144 and 126 form a “DSP”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a trans-impedance amplifier (TIA) to the receiver of an optical transceiver of Movassaghi et al. in view of Gareau et al. in order to ensure that the received signal has sufficient voltage/amplitude for subsequent processing.
With regard to claim 14, Movassaghi et al. in view of Gareau et al. disclose the claimed invention except for receiving, at the second DSP, a second trans-impedance amplifier (TIA) output from a second (TIA). FIG. 3 of Zhang discloses a transceiver with a trans-impedance amplifier (TIA) (see 142) that provides an output to a “DSP” (wherein 144 and 126 form a “DSP”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a trans-impedance amplifier (TIA) to the receiver of an optical transceiver of Movassaghi et al. in view of Gareau et al. in order to ensure that the received signal has sufficient voltage/amplitude for subsequent processing.
With regard to claim 20, Movassaghi et al. in view of Gareau et al. disclose the claimed invention except for the first DSP is operable to receive, at the first optical receiver coupled to the first DSP, a first trans-impedance amplifier (TIA) output from a first (TIA). FIG. 3 of Zhang discloses a transceiver with a trans-impedance amplifier (TIA) (see 142) that provides an output to a “DSP” (wherein 144 and 126 form a “DSP”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a trans-impedance amplifier (TIA) to the receiver of an optical transceiver of Movassaghi et al. in view of Gareau et al. in order to ensure that the received signal has sufficient voltage/amplitude for subsequent processing.
Conclusion
Please note that non-cited portions of the references may also read on the claim limitations. Therefore, the references should be considered in their entirety.
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/BETSY DEPPE/Primary Examiner, Art Unit 2633
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