DETAILED ACTION
Application filed 3/17/2025 has been examined.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-5 are pending.
Specification and drawings are accepted.
IDSs have been considered. PTO-1449s are attached.
Application is pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5 of U.S. Patent No. 12,283,971.
Although the claims at issue are not identical, they are not patentably distinct from each other. For example, claim 1 of the present application teaches a flash memory controller coupled to a flash memory module comprising a plurality of first blocks and at least one second block, wherein the flash memory controller is configured to: classify data into a plurality of groups, and perform an error code encoding operation on the groups of data to generate corresponding parity check code; write the groups of data and the corresponding parity check code into the plurality of first blocks of the flash memory module according to a randomizer seed rule of the at least one second block; after the groups of data are written into the plurality of first blocks, control the flash memory module to move the groups of data and corresponding parity check code from the plurality of first blocks to the at least one second block. Whereas claim 1 of U.S. patent ‘971 teaches a method for accessing a flash memory module, wherein the flash memory module comprises a plurality of first blocks and at least one second block, and the method comprises the steps of: classifying data into a plurality of groups; performing an error code encoding operation on the groups of data to generate corresponding parity check code; writing the groups of data and the corresponding parity check code into the plurality of first blocks of the flash memory module according to a randomizer seed rule of the at least one second block; and after the groups of data are written into the plurality of first blocks, writing the groups of data and corresponding parity check code from the plurality of first blocks to the at least one second block. Both claims are generally directed towards flash memory with first blocks and second block, classification of the data, error correction code and writing of the data. The claims are both drawn to obvious embodiments of each other and not patentably distinct. A terminal disclaimer would obviate the rejection.
Claims 1-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 11,916,569.
Although the claims at issue are not identical, they are not patentably distinct from each other. For example, claim 1 of the present application teaches a flash memory controller coupled to a flash memory module comprising a plurality of first blocks and at least one second block, wherein the flash memory controller is configured to: classify data into a plurality of groups, and perform an error code encoding operation on the groups of data to generate corresponding parity check code; write the groups of data and the corresponding parity check code into the plurality of first blocks of the flash memory module according to a randomizer seed rule of the at least one second block; after the groups of data are written into the plurality of first blocks, control the flash memory module to move the groups of data and corresponding parity check code from the plurality of first blocks to the at least one second block. Whereas claim 1 of U.S. patent ‘569 teaches a flash memory apparatus, comprising: a flash memory module comprising a plurality of first blocks and at least one second block; and a flash memory controller having a plurality of channels respectively connected to the flash memory module, wherein the flash memory controller is configured to classify data into a plurality of groups, perform an error code encoding operation on the groups of data to generate corresponding parity check code, and write the groups of data and the corresponding parity check code into the plurality of first blocks of the flash memory module according to a randomizer seed rule of the at least one second block; wherein after the groups of data are written into the plurality of first blocks, the flash memory module writes the groups of data and corresponding parity check code from the plurality of first blocks to the at least one second block. Both claims are generally directed towards flash memory with first blocks and second block, classification of the data, error correction code and writing of the data. The claims are both drawn to obvious embodiments of each other and not patentably distinct. A terminal disclaimer would obviate the rejection.
Claims 1-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 11,323,133.
Although the claims at issue are not identical, they are not patentably distinct from each other. For example, claim 1 of the present application teaches a flash memory controller coupled to a flash memory module comprising a plurality of first blocks and at least one second block, wherein the flash memory controller is configured to: classify data into a plurality of groups, and perform an error code encoding operation on the groups of data to generate corresponding parity check code; write the groups of data and the corresponding parity check code into the plurality of first blocks of the flash memory module according to a randomizer seed rule of the at least one second block; after the groups of data are written into the plurality of first blocks, control the flash memory module to move the groups of data and corresponding parity check code from the plurality of first blocks to the at least one second block. Whereas claim 1 of U.S. patent ‘133 teaches a flash memory apparatus, comprising: a flash memory module comprising a plurality of first blocks and at least one second block; and a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing a specific programing and a specific error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of first blocks; wherein when programming data into the plurality of first blocks, the flash memory controller is arranged to program data into the plurality of first blocks according to a randomizer seed rule of the at least one second block; and. when completing program of the plurality of first blocks, the flash memory module programs the at least one second block of the flash memory module according to the plurality of first blocks of the flash memory module. Both claims are generally directed towards flash memory with first blocks and second block, classification of the data, error correction code and writing of the data. The claims are both drawn to obvious embodiments of each other and not patentably distinct. A terminal disclaimer would obviate the rejection.
Claims 1-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 10,771,091.
Although the claims at issue are not identical, they are not patentably distinct from each other. For example, claim 1 of the present application teaches a flash memory controller coupled to a flash memory module comprising a plurality of first blocks and at least one second block, wherein the flash memory controller is configured to: classify data into a plurality of groups, and perform an error code encoding operation on the groups of data to generate corresponding parity check code; write the groups of data and the corresponding parity check code into the plurality of first blocks of the flash memory module according to a randomizer seed rule of the at least one second block; after the groups of data are written into the plurality of first blocks, control the flash memory module to move the groups of data and corresponding parity check code from the plurality of first blocks to the at least one second block. Whereas claim 1 of U.S. patent ‘091 teaches a flash memory apparatus, comprising: a flash memory module comprising a plurality of first blocks and at least one second block; and a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programing and RAID-like (Redundant Array of Independent Disks-like) RS (Reed-Solomon) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of first blocks; wherein when completing program of the plurality of first blocks, controlling the flash memory module to perform an internal copy operation to program the at least one second block of the flash memory module according to the plurality of first blocks of the flash memory module; a cell of one first block is used for storing a data amount smaller than a data amount stored by a cell of one second block. Both claims are generally directed towards flash memory with first blocks and second block, classification of the data, error correction code and writing of the data. The claims are both drawn to obvious embodiments of each other and not patentably distinct. A terminal disclaimer would obviate the rejection.
Claims 1-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 10,236,908.
Although the claims at issue are not identical, they are not patentably distinct from each other. For example, claim 1 of the present application teaches a flash memory controller coupled to a flash memory module comprising a plurality of first blocks and at least one second block, wherein the flash memory controller is configured to: classify data into a plurality of groups, and perform an error code encoding operation on the groups of data to generate corresponding parity check code; write the groups of data and the corresponding parity check code into the plurality of first blocks of the flash memory module according to a randomizer seed rule of the at least one second block; after the groups of data are written into the plurality of first blocks, control the flash memory module to move the groups of data and corresponding parity check code from the plurality of first blocks to the at least one second block. Whereas claim 1 of U.S. patent ‘908 teaches a flash memory apparatus, comprising: a flash memory module comprising a plurality of single-level-cell blocks and at least one multiple-level-cell block; and a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) RS (Reed-Solomon) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of single-level-cell blocks; wherein when completing program of the plurality of single-level-cell blocks, controlling the flash memory module to perform an internal copy operation to program the at least one multiple-level-cell block of the flash memory module according to the plurality of single-level-cell blocks of the flash memory module. Both claims are generally directed towards flash memory with first blocks and second block, classification of the data, error correction code and writing of the data. The claims are both drawn to obvious embodiments of each other and not patentably distinct. A terminal disclaimer would obviate the rejection.
Conclusion
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MUJTABA M. CHAUDRY
Primary Examiner
Art Unit 2112
/MUJTABA M CHAUDRY/Primary Examiner, Art Unit 2112
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