Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are now pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Information Disclosure Statement
The information disclosure statement filed 03/17/2025 fails to comply with 37 CFR 1.98(a)(1), which requires the following: (1) a list of all patents, publications, applications, or other information submitted for consideration by the Office; (2) U.S. patents and U.S. patent application publications listed in a section separately from citations of other documents; (3) the application number of the application in which the information disclosure statement is being submitted on each page of the list; (4) a column that provides a blank space next to each document to be considered, for the examiner’s initials; and (5) a heading that clearly indicates that the list is an information disclosure statement. The information disclosure statement has been placed in the application file, but the information referred to therein has not been considered.
The information disclosure statement filed 04/28/2025 has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent 12,277,064. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of U.S. Patent 12,277,064 recite features, indistinct in content of claims 1-20 of the instant application (19/081,379).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have been allowed, but not in fact been patented.
Claim 1 (US Application 19/081,379)
Claim 16 (U.S. Patent 12,277,064)
A memory system, comprising:
a memory device; and
a memory controller,
wherein the memory controller is coupled to the memory device, the memory device comprising a first space and a second space,
a storage mode of the first space being a first mode, a storage mode of the second space being a second mode, a write speed of the second mode being lower than that of the first mode; and
the memory controller is configured to: in response to a flush command, configure a part of a free space of the memory device as an available space of the first space, the free space of the memory device comprising a free space in the first space and a free space in the second space; and update a parameter representing the available space of the first space.
A memory system, comprising:
a memory device; and
a memory controller,
wherein the memory controller is coupled to the memory device, the memory device having a first space and a second space, the first space having an initial size,
a storage mode of the first space being a first mode, and a storage mode of the second space being a second mode, a write speed of the second mode being lower than that of the first mode; and
the memory controller is configured to: in response to a first space flush command for performing a flush operation that empties the first space, restore an available size of the first space to the initial size of the first space by configuring a part of a free space of the memory device as an available space of the first space in a case where a size of the free space is greater than or equal to a first threshold, the free space of the memory device including a free space in the first space and a free space in the second space.
Claim 16 (US Application 19/081,379)
Claim 1 (U.S. Patent 12,277,064)
A method for operating a memory system, the memory system comprising a memory controller and a memory device, the memory controller being coupled to the memory device, the memory device comprising a first space and a second space, a storage mode of the first space being a first mode, and a storage mode of the second space being a second mode, a write speed of the second mode being lower than that of the first mode, the method comprising:
in response to a flush command, configuring a part of a free space of the memory device as an available space of the first space, the free space of the memory device comprising a free space in the first space and a free space in the second space; and updating a parameter representing the available space of the first space.
A method for operating a memory system, the memory system comprising a memory controller and a memory device, the memory controller being coupled to the memory device, the memory device having a first space and a second space, the first space having an initial size, a storage mode for the first space being a first mode, a storage mode for the second space being a second mode, a write speed of the second mode being lower than that of the first mode, the method comprising:
in response to a first space flush command for performing a flush operation that empties the first space, restoring an available size of the first space to the initial size of the first space by configuring a part of a free space of the memory device as an available space of the first space in a case where a size of the free space is greater than or equal to a first threshold, the free space of the memory device including a free space in the first space and a free space in the second space.
.
Regarding claim 1 of the claimed invention, while claim 1 of the instant application and claim 16 of the patent differ in words, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize that “configuring a part of a free space of the memory device as an available space of the first space” in claim 1 (claimed invention) is logically modified to recite “restoring an available size of the first space to the initial size of the first space by configuring a part of a free space of the memory device as an available space of the first space” of claim 16 of U.S. Patent 12,277,064.
Similarly, regarding claim 16 of the claimed invention, while claim 16 of the instant application and claim 1 of the patent differ in words it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize that “configuring a part of a free space of the memory device as an available space of the first space” in claim 16 (claimed invention) s logically modified to recite “restoring an available size of the first space to the initial size of the first space by configuring a part of a free space of the memory device as an available space of the first space” of claim 1 of U.S. Patent 12,277,064.
The two, which appear to be the different features in words, are similar in content or the two applications would have been obvious variation of one in view of the other because: commonly linked to the recitations:
“configuring a part of a free space of the memory device as an available space of the first space” (claimed application) and
“restoring an available size of the first space to the initial size of the first space by configuring a part of a free space of the memory device as an available space of the first space” (US Patent)
is
“free space of the memory device comprising a free space in the first space and a free space in the second space” which is essential to the two recitations.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a2) as being anticipated by US 20230043338 A1 (BI).
With respect to claim 1, BI teaches memory system, comprising: a memory device; and a memory controller, wherein the memory controller is coupled to the memory device (memory system including memory system controller to perform functions ascribed to the memory system controller) [Fig. 1; Par. 0023; Par. 0019-0022], the memory device comprising a first space and a second space, a storage mode of the first space being a first mode, a storage mode of the second space being a second mode, a write speed of the second mode being lower than that of the first mode (memory system including memory system controller to perform functions ascribed to the memory system controller) [Fig. 1; Par. 0023; Par. 0019-0022] (the memory devices may refer to portions (zones) or sets of memory cells configured to store date and portions configured to store stale data referred to as a stale zone memory device also refers to a single-level cell (SLC) block and tri-level cell (TLC) block) different write speed from the single level cell (SLC)) [Par. 0010-0011]; and the memory controller is configured to: in response to a flush command, configure a part of a free space of the memory device as an available space of the first space, the free space of the memory device comprising a free space in the first space and a free space in the second space (in response to receiving a command to remove at least a portion of the recent data (e.g., an unmap command a flush operation),i.e., flush operation to transfer data from one set of memory cells to a second set of memory cells (e.g., transfer data from a single-level cell (SLC) block to a tri-level cell (TLC) block), determine a size of data satisfying a threshold (e.g., a size of data to be removed indicated in the unmap command) and the size indicating an amount of available space, the size of the stale zone to include the available space, the memory device indicating the current stale zone size set compared to a default zone size or to a size determined by a previous size of data to be removed) [Par. 0010-011; Par. 0081-0086; Par.0107-0112]; and update a parameter representing the available space of the first space (the memory controller to record the available amount, parameters indicating available size where, associated with received command such as an unmap command or a flush operation, updating the size of the stale zone in response to the memory system receiving a command) [Abstract; Par.0089-0091; Par. 0067-0069; Par. 0076-0077].
With respect to claim 9, BI teaches system, comprising: a host; and a memory system comprising a memory controller coupled to the host and a memory device coupled to the memory controller (memory system including memory system controller or, in alternative, a memory system alternatively relying upon an external controller (e.g., implemented by the host system) or one or more local controllers, which may be internal to memory devices, respectively, to perform the functions ascribed to the memory system controller) [Fig. 1; Par. 0023; Par. 0019-0022], wherein the host is configured to send a flush command based on a current available space of a first space, the memory device comprising the first space and a second space, a storage mode of the first space being a first mode, and a storage mode of the second space being a second mode, a write speed of the second mode being lower than that of the first mode (the memory devices may refer to portions (zones) or sets of memory cells configured to store date and portions configured to store stale data referred to as a stale zone memory device also refers to a single-level cell (SLC) block and tri-level cell (TLC) block) different write speed from the single level cell (SLC)) [Par. 0010-0011]; and the memory controller is configured to: receive the flush command, and configure a part of a free space of the memory device as an updated available space of the first space, the free space of the memory device comprising a free space in the first space and a free space in the second space (in response to receiving a command to remove at least a portion of the recent data (e.g., an unmap command a flush operation),i.e., flush operation to transfer data from one set of memory cells to a second set of memory cells (e.g., transfer data from a single-level cell (SLC) block to a tri-level cell (TLC) block), determine a size of data satisfying a threshold (e.g., a size of data to be removed indicated in the unmap command) and the size indicating an amount of available space, the size of the stale zone to include the available space, the memory device indicating the current stale zone size set compared to a default zone size or to a size determined by a previous size of data to be removed) [Par. 0010-011; Par. 0081-0086; Par.0107-0112]; and send a parameter representing the updated available space of the first space to the host (the memory controller to record the available amount, parameters indicating available size where, associated with received command such as an unmap command or a flush operation, updating the size of the stale zone in response to the memory system receiving a command) [Abstract; Par.0089-0091; Par. 0067-0069; Par. 0076-0077].
With respect to claim 16, BI teaches method for operating a memory system, the memory system comprising a memory controller and a memory device, the memory controller being coupled to the memory device (memory system including memory system controller to perform functions ascribed to the memory system controller) [Fig. 1; Par. 0023; Par. 0019-0022], the memory device comprising a first space and a second space, a storage mode of the first space being a first mode, and a storage mode of the second space being a second mode, a write speed of the second mode being lower than that of the first mode (the memory devices may refer to portions (zones) or sets of memory cells configured to store date and portions configured to store stale data referred to as a stale zone memory device also refers to a single-level cell (SLC) block and tri-level cell (TLC) block) different write speed from the single level cell (SLC)) [Par. 0010-0011], the method comprising: in response to a flush command, configuring a part of a free space of the memory device as an available space of the first space, the free space of the memory device comprising a free space in the first space and a free space in the second space (in response to receiving a command to remove at least a portion of the recent data (e.g., an unmap command a flush operation),i.e., flush operation to transfer data from one set of memory cells to a second set of memory cells (e.g., transfer data from a single-level cell (SLC) block to a tri-level cell (TLC) block), determine a size of data satisfying a threshold (e.g., a size of data to be removed indicated in the unmap command) and the size indicating an amount of available space, the size of the stale zone to include the available space, the memory device indicating the current stale zone size set compared to a default zone size or to a size determined by a previous size of data to be removed) [Par. 0010-011; Par. 0081-0086; Par.0107-0112]; and updating a parameter representing the available space of the first space (function of the memory controller that records the available amount, parameters indicating available size where, associated with received command such as an unmap command or a flush operation, updating the size of the stale zone in response to the memory system receiving a command) [Abstract; Par.0089-0091; Par. 0067-0069; Par. 0076-0077].
With respect to claims 2, 10, and 17, BI teaches memory system and method for operating a memory system, wherein the memory controller includes a random access memory, the random access memory stores the parameter (the memory controller including storage registers to store the size information) [Par. 0088-0089].
With respect to claims 3, 11, and 18, BI teaches memory system and method for operating a memory system,, wherein the parameter comprises an occupancy ratio, the occupancy ratio being calculated as a ratio of a size of the available space to an initial size of the first space (memory controller to configured the available stale zone size based on the current stale zone size and a default available size (e.g., the difference between the current stale zone size and the default deleted stale data size the last daily delete TLC data size)) [Par. 0084-0085; Par. 0091-0094].
With respect to claims 4, 12, and 19, BI teaches memory system and method for operating a memory system,, wherein the memory controller configures the part of the free space as the available space of the first space if a size of the free space is greater than or equal to a threshold (the controller determining available size corresponding to amount of space based on deleted data size being greater than a threshold) [Par. 0082-0084].
With respect to claims 5, 13, and 20, BI teaches memory system and method for operating a memory system,, wherein the memory controller is further configured to store data in the first mode into the free space in the second mode if the size of the free space is smaller than the threshold (storage controller to retrieve information determining sufficient available space for storage compared to a threshold ) [Par. 0067-0069; Par. 0073-0077; Par. 0062-0064; 0054-0055].
With respect to claims 6 and 14, BI teaches memory system and method for operating a memory system,, wherein the threshold is equal to the initial size of the first space (size of the stale zone determined based on an available zone size, adjusted to the default stale zone size) [Par. 0035-0036].
With respect to claims 7 and 15, BI teaches memory system and method for operating a memory system,, wherein the size of the available space of the first space is an initial value after the part of the free space is configured as the available space of the first space (an amount of available space set as free zone set the size of the stale zone to include the available space) [Par. 0011; Par. 0067-0069; Par. 0034-0035; Par. 0073-0077].
With respect to claim 8, BI teaches memory system and method for operating a memory system,, wherein the first mode comprises a single- level cell (SLC) mode, and the second mode includes a multi-level cell (MLC) mode, a three- level cell (TLC) mode, or a quad-level cell (QLC) mode (mapping mode including single-level cell (SLC) block and tri-level cell (TLC) block) [Par. 0067-0069; Par. 0010-0011; Par. 0027; Par. 0073-0077].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 12321620 B2 (BI) teaching methods, systems, and devices for techniques for memory zone size adjustment of a memory system dynamically updated the size of a stale zone configured to store data written during a write burst or write booster mode.
US 20240232067 A1 - US 12265468 B2 (WU et al) teaching method including: utilizing a memory controller to set at least one write booster static parameter of a write booster function of the memory device; utilizing the memory controller to perform device initialization corresponding to at least one initialization phase of the memory device; and after completing the device initialization corresponding to the at least one initialization phase, performing at least one adaptive flag-setting operation, for setting at least one write booster flag among a plurality of write booster flags of the write booster function, wherein the at least one write booster flag includes a first write booster flag acting as a write booster switch., the adaptive flag-setting operation includes setting the first write booster flag to enable the write booster function by default.
B. Akesson et al., "Memory controllers for high-performance and real-time MPSoCs requirements, architectures, and future trends," 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Taipei, Taiwan, 2011, pp. 3-12.
D. Liu, K. Zhong, X. Zhu, Y. Li, L. Long and Z. Shao, "Non-Volatile Memory Based Page Swapping for Building High-Performance Mobile Devices," in IEEE Transactions on Computers, vol. 66, no. 11, pp. 1918-1931, 1 Nov. 2017.
S. Ghandeharizadeh, S. Irani and J. Lam, "On Configuring a Hierarchy of Storage Media in the Age of NVM," 2018 IEEE 34th International Conference on Data Engineering (ICDE), Paris, France, 2018, pp. 1380-1383.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138
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