DETAILED ACTION
This action is responsive to the following: the claims filed on March 17, 2025 and April 29, 2025 and the information disclosure statements filed on February 26, 2026 and May 1, 2026.
Claims 1-20 are pending. Claims 1, 11, and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 10-14, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al (US 20230065104 A1).
Regarding Independent Claim 1, Lin teaches a memory circuit (Fig. 2: 200), comprising:
a first memory cell (Fig. 2: 202) and a second memory cell (Fig. 2: 212) coupled to a first sense amplifier (Fig. 2: 108) through a first bit line and a second bit line, respectively;
a third memory cell (Fig. 2: 202) and a fourth memory cell (Fig. 2: 212) coupled to a second sense amplifier (Fig. 2: 108) through a third bit line and a fourth bit line, respectively (persons skilled in the memory art would understand circuit 200 in Figure 2 is exemplary of circuitry for two adjacent bit lines, and would be repeated throughout a memory array for each pair of bit lines in the memory array coupled to a sense amplifier just like Figure 2.); and
a reference circuit (Fig. 2: 112) configured to provide a plurality of reference current levels corresponding to different operation modes of any of the first to fourth memory cells (Fig. 2: 202, 212), respectively;
wherein the reference circuit (Fig. 2: 112) is alternately coupled to the first bit line and the third bit line or coupled to the second bit line and the fourth bit line. (para 25-26 “For example, if the sense amplifier circuit 108 is configured to perform a read operation on the RRAM_L cell 202, the sense amplifier circuit 108 receives the left-side RRAM device path and the self-tracking reference circuit as the two inputs. The clamping devices 206 and 216 are turned on by VCL to define the read voltage level. Such a configuration can be achieved by turning on the transistor device 208 to enable the access path 204 to connect the RRAM_L cell 202 to the sense amplifier circuit 108. Additionally, the self-tracking reference circuit path can be configured to be the second input of the sense amplifier circuit 108 by turning on the transistor device, while turning off the transistor devices 222 and 218. Such a configuration creates a path where the configurable resistor network 112 is connected to the sense amplifier circuit 108 through the access path including transistor devices 224 and 216. The access path 214 connecting the RRAM_R cell 212 to the sense amplifier circuit 108 is disabled.
On the other hand, for example, if the sense amplifier circuit 108 is configured to perform a read operation on the RRAM_R cell 212, the sense amplifier circuit 108 receives the right-side RRAM device path and the self-tracking reference circuit as the two inputs. The clamping devices 206 and 216 are turned on by VCL to define the read voltage level. Such a configuration can be achieved by turning on the transistor device 218 to enable the access path 214 to connect the RRAM_R cell 212 to the sense amplifier circuit 108. Additionally, the self-tracking reference circuit path can be configured to be the second input of the sense amplifier circuit 108 by turning on the transistor device 222, while turning off the transistor devices 224 and 208. Such a configuration creates a path where the configurable resistor network 112 is connected to the sense amplifier circuit 108 through the access path including transistor devices 222 and 206. The access path 204 connecting the RRAM_L cell 202 to the sense amplifier 108 is disabled.”)
Regarding Claim 2, Lin teaches the limitations of Claim 1. Lin further teaches wherein each of the first to fourth memory cells (Fig. 2: 202, 212) includes a resistive random access memory (RRAM) cell (Fig. 2: RRAM_L, RRAM_R).
Regarding Claim 3, Lin teaches the limitations of Claim 1. Lin further teaches wherein the reference circuit (Fig. 2: 112) includes a first resistor (Fig. 3b: 316), a second resistor (Fig. 3b: 318), a third resistor (Fig. 3b: 320), and a transistor array (Fig. 3b: 116) connected in series.
Regarding Claim 4, Lin teaches the limitations of Claim 3. Lin further teaches wherein the transistor array includes one transistor (Fig. 4A: 116), four transistors (Fig. 4B: 116), nine transistors (Fig. 4C: 116), or sixteen transistors (para 40 “ For different application, different implementations may also provide the best tradeoff between current variation and layout area.”).
Regarding Claim 10, Lin teaches the limitations of Claim 1. Lin further teaches wherein the different operation modes include a normal read, a first write verification, and a second write verification (para 13 “The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator to provide a PVT tracking level for verify and normal read operation”) of each of the first to fourth memory cells (Fig. 2: 202, 212) .
Regarding Independent Claim 11, Lin teaches A memory circuit (Fig. 2: 200), comprising:
a first memory cell (Fig. 2: 202) and a second memory cell (Fig. 2: 212) coupled to a first sense amplifier (Fig. 2: 108) through a first bit line and a second bit line, respectively;
a third memory cell (Fig. 2: 202) and a fourth memory cell (Fig. 2: 212) coupled to a second sense amplifier (Fig. 2: 108) through a third bit line and a fourth bit line, respectively (persons skilled in the memory art would understand circuit 200 in Figure 2 is exemplary of circuitry for two adjacent bit lines, and would be repeated throughout a memory array for each pair of bit lines in the memory array coupled to a sense amplifier just like Figure 2), wherein the first to fourth memory cells (Fig. 2: 202, 212) are each configured to present a first resistance state or a second resistance state (para 53 “Based on the comparison of the current values, the data value stored in the RRAM cell can be read. For example, a high resistance state may indicate a logic “0” value, and a low resistance state may indicate a logic “1” value. Other methods of reading the RRAM cell data is also possible.”); and
a reference circuit (Fig. 2: 112) configured to provide a plurality of reference current levels for both of the first and second sense amplifiers (Fig. 2: 108).
Regarding Claim 12, Lin teaches the limitations of Claim 11. Lin further teaches wherein a first one of the plurality of reference current levels (para 30 “The configurable resistor network 112, which has less temperature dependency than the RRAM resistive element, emulates the RRAM element and provides the set verify level, the reset verify level and normal read levels.”) corresponds to reading any of the first to fourth memory cells (Fig. 2: 202, 212) , a second one of the plurality of reference current levels corresponds to verifying whether the first resistance state is written to any of the first to fourth memory cells (Fig. 2: 202, 212) , and a third one of the plurality of reference current levels corresponds to verifying whether the second resistance state is written to any of the first to fourth memory cells (Fig. 2: 202, 212).
Regarding Claim 13, Lin teaches the limitations of Claim 11.Claim 13 is rejected for the same reasons as claim 3.
Regarding Claim 14, Lin teaches the limitations of Claim 13. Claim 14 is rejected for the same reasons as claim 4.
Regarding Independent Claim 19, Lin teaches A method for operating memory circuits (Fig. 2: 200), comprising:
activating a first group of switches (Fig. 2: 214, 224) to couple a first bit line and a second bit line (Fig. 2: 212, 220) to a reference circuit (Fig. 2: 112), while deactivating a second group of switches (Fig. 2: 204, 222), so as to decouple a third bit line and a fourth bit line (Fig. 2: 202, 210) each from the reference circuit (Fig. 2: 112; persons skilled in the memory art would understand circuit 200 in Figure 2 is exemplary of circuitry for two adjacent bit lines, and would be repeated throughout a memory array for each pair of bit lines in the memory array coupled to a sense amplifier just like Figure 2), wherein the reference circuit (Fig. 2: 112) is configured to provide a plurality of reference current levels (para 30 “The configurable resistor network 112, which has less temperature dependency than the RRAM resistive element, emulates the RRAM element and provides the set verify level, the reset verify level and normal read levels.”);
comparing a first cell current (Fig. 2: 118) flowing through a first one of a plurality of memory cells (Fig. 2: 212) with a first one of the plurality of reference current levels, wherein the first memory cell (Fig. 2: 202) is coupled to a first sense amplifier (Fig. 2: 108) through the third bit line or the fourth bit line (Fig. 2: 202, 210);
deactivating the first group of switches (Fig. 2: 214, 224) to decouple the first bit line and the second bit line (Fig. 2: 212, 220) each from the reference circuit (Fig. 2: 112), while activating the second group of switches (Fig. 2: 204, 222) to couple the third bit line and the fourth bit line (Fig. 2: 202, 210) to the reference circuit (Fig. 2: 112); and
comparing a second cell current flowing (Fig. 2: 118) through a second one of the plurality of memory cells (Fig. 2: 202) with a second of the plurality of reference current levels, wherein the second memory cell (Fig. 2: 212) is coupled to a second sense amplifier (Fig. 2: 108) through the first bit line or the second bit line (Fig. 2: 204, 220).
(para 25-26 “For example, if the sense amplifier circuit 108 is configured to perform a read operation on the RRAM_L cell 202, the sense amplifier circuit 108 receives the left-side RRAM device path and the self-tracking reference circuit as the two inputs. The clamping devices 206 and 216 are turned on by VCL to define the read voltage level. Such a configuration can be achieved by turning on the transistor device 208 to enable the access path 204 to connect the RRAM_L cell 202 to the sense amplifier circuit 108. Additionally, the self-tracking reference circuit path can be configured to be the second input of the sense amplifier circuit 108 by turning on the transistor device, while turning off the transistor devices 222 and 218. Such a configuration creates a path where the configurable resistor network 112 is connected to the sense amplifier circuit 108 through the access path including transistor devices 224 and 216. The access path 214 connecting the RRAM_R cell 212 to the sense amplifier circuit 108 is disabled.
On the other hand, for example, if the sense amplifier circuit 108 is configured to perform a read operation on the RRAM_R cell 212, the sense amplifier circuit 108 receives the right-side RRAM device path and the self-tracking reference circuit as the two inputs. The clamping devices 206 and 216 are turned on by VCL to define the read voltage level. Such a configuration can be achieved by turning on the transistor device 218 to enable the access path 214 to connect the RRAM_R cell 212 to the sense amplifier circuit 108. Additionally, the self-tracking reference circuit path can be configured to be the second input of the sense amplifier circuit 108 by turning on the transistor device 222, while turning off the transistor devices 224 and 208. Such a configuration creates a path where the configurable resistor network 112 is connected to the sense amplifier circuit 108 through the access path including transistor devices 222 and 206. The access path 204 connecting the RRAM_L cell 202 to the sense amplifier 108 is disabled.”)
Regarding Claim 20, Lin teaches the limitations of Claim 19. Lin further teaches wherein the plurality of reference current levels correspond to different operation modes of any of the plurality of memory cells, respectively (para 13 “The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator to provide a PVT tracking level for verify and normal read operation”).
Allowable Subject Matter
Claims 5-9 and 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 5, 8, 15, and 17 are allowable for teachings switches connecting separate bit lines connected to different sense amplifiers to each other as recited in those respective claims. Lin teaches switches between the bit lines and reference resistances, but fails to teach switches between bit lines connected to different sense amplifiers. Therefore, these claims would be allowable if written in independent form.
Conclusion
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
