DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 20, 21, 22, 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Delshadpour et al (US 11,206,161) in view of Liao et al (US 2016/0352557) (IDS). a) Regarding claim 1, Delshadpour et al disclose a re-driver comprising:
a programmable linear equalizer (402 in Fig. 4) capable of equalizing a transmitted analog signal to generate an equalized signal (Col 4, L37-41);
a variable gain amplifier (404) capable of amplifying the equalized signal to produce an amplified signal (Col 4, L41-44);
a line driver (406) capable of generating an output signal based upon the amplified signal (Col 4, L45-47); and
digital link adaptation circuitry (412) capable of: programming the programmable linear equalizer (412; Col 5, L29-47).
Delshadpour et al disclose a continuous time linear equalization (CTLE) with a feedback loop of an adaptative controller. Delshadpour et al did not explicitly teach sampling the amplified signal to produce a sampled signal and generating programming parameters for the programmable linear equalizer based upon the sampled signal.
However, Liao et al disclose a receiver system comprising a CTLE (103) coupled to an ADC (105 in Fig. 1) (Pub [0025-0027]). The CTLE also receives a CTLE adapt (156) as a feedback control, which is based on the output of the ADC (Pub [0041]). The channel adaptive ADC in a receiver would accommodate dynamical change of the transmission channel conditions. Thus, to achieve a target error rate (Pub [0002]). Therefore, it is obvious to one of ordinary skill in the art before the filling date of the claimed invention to combine the ADC sampling of Liao et al with the CTLE and adaptive controller of Delshadpour et al. The feedback control loop of CTLE would include sampling the amplified signal to produce a sampled signal and generating programming parameters for the programmable linear equalizer based upon the sampled signal. By doing so, facilitate and accommodate dynamical change of the transmission channel conditions. Thus, to achieve a target error rate. b) Regarding claim 2, Delshadpour et al disclose wherein: the variable gain amplifier is a programmable variable gain amplifier (404 in Fig. 4; Col 4, L41-44); and the digital link adaptation circuitry is further capable of: generating programming parameters for the programmable variable gain amplifier (412); and programming the programmable variable gain amplifier (412; Col 5, L29-47). Liao et al disclose generating programming parameters for the programmable variable gain amplifier based upon the sampled signal (Fig. 1; Pub [0025-0027], [0041]). c) Regarding claim 20, Liao et al disclose wherein digital link adaptation circuitry is configurable to obtain a sampling clock signal by: recovering the sampling clock signal from the sampled signal (151 in Fig. 1); or receiving, via an input, the sampling clock signal from a synchronous clock source or a synchronous neighboring channel (“or” is an optional statement).
d) Regarding claim 21, Liao et al disclose further comprising a skew adjuster (151 in Fig. 8; phase interpolator and phase error detector in CDR controls skewing). e) Regarding claim 22, Delshadpour et al and Liao et al in combination teach the programmable linear equalizer (420 in Delshadpour et al), the variable gain amplifier (404), the line driver (406), and the digital link adaptation circuitry (412). Delshadpour et al and Liao et al did not explicitly teach a content management interoperability services (CMIS) interface. However, CMIS interface is a standard interface that enables different content management system to interoperate. Therefore, it is obvious to one of ordinary skill in the art before the filling date of the claimed invention to combine the teaching of Delshadpour et al and Liao et al with CMIS interface. By doing so, facilitate signal receiving, equalization and processing.
f) Regarding claim 25, Delshadpour et al disclose digital link adaptation circuitry (412 in Fig. 4). Liao et al disclose an analog to digital converter (105 in Fig. 1; Pub [0025-0027]). Liao et al did not explicitly teach the ADC is a 12-bit converter. However, a 12-bit ADC converter is well known and widely used for a wide range of applications. Therefore, it is obvious to one of ordinary skill in the art before the filling date of the claimed invention to apply a 12-bit ADC of Liao et al. By doing so, provide equalization and signal processing in a communication system. g) Regarding claim 26, Delshadpour et al disclose wherein the programming parameters removes inter-symbol interference in a communication channel (Col 4, L65- Col 5, L28).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Delshadpour et al (US 11,206,161) in view of Liao et al (US 2016/0352557) (IDS), and in further view of Nguyen et al (US 2025/0233781). a) Regarding claim 10, Delshadpour et al and Liao et al in combination teach the programmable linear equalizer (420 in Delshadpour et al), the variable gain amplifier (404), the line driver (406), and the digital link adaptation circuitry (412). Delshadpour et al and Liao et al did not explicitly teach they are formed on a single integrated circuit.
However, Nguyen et al disclose CTLE and control range (Fig. 1 and 2). The entirety of the circuits maybe implemented in a single integrated circuit (IC) chip (Pub [0027]). An IC is well known for compact size and low cost in electronic circuit design. Therefore, it is obvious to one of ordinary skill in the art before the filling date of the claimed invention to combine the CTLE and adaptive controller of Delshadpour et al and Liao et al with the single integrated circuit (IC) chip teaching of Nguyen et al. By doing so, optimize size, reduce cost and achieve high reliability in a communication system.
Claims 11, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Delshadpour et al (US 11,206,161) in view of Liao et al (US 2016/0352557) (IDS), and in further view of Gao et al (US 2025/0076958). a) Regarding claim 11, Delshadpour et al disclose digital link adaptation circuitry (412 in Fig. 4). Liao et al disclose an analog to digital converter (105 in Fig. 1; Pub [0025-0027]). Delshadpour et al and Liao et al did not explicitly teach a microcontroller unit (MCU).
However, Gao et al disclose CTLE is managed by a microcontroller (Fig. 3A and 3B; Pub [0031]). A microcontroller is a single electronic chip for managing specific functions in electronic devices. It optimizes embedded applications. Therefore, it is obvious to one of ordinary skill in the art before the filling date of the claimed invention to combine the CTLE of Delshadpour et al and ADC of Liao et al with the microcontroller teaching of Gao et al. By doing so, reduce cost and energy, and optimize control functions for a wide range of electronic devices and embedded applications. b) Regarding claim 13, Delshadpour et al disclose digital link adaptation circuitry (412 in Fig. 4). Liao et al disclose an analog to digital converter (105 in Fig. 1; Pub [0025-0027]). Liao et al did not explicitly teach the ADC is a 12-bit converter. However, a 12-bit ADC converter is well known and widely used for a wide range of applications. Therefore, it is obvious to one of ordinary skill in the art before the filling date of the claimed invention to apply a 12-bit ADC of Liao et al. By doing so, provide equalization and signal processing in a communication system. c) Regarding claim 14, Liao et al disclose wherein digital link adaptation circuitry is further capable of recovering a sampling clock signal from the sampled signal (151 in Fig. 1).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Delshadpour et al (US 11,206,161) in view of Liao et al (US 2016/0352557) (IDS), in further view of Gao et al (US 2025/0076958), and further in view of Nguyen et al (US 2025/0233781). a) Regarding claim 12, Delshadpour et al disclose the programmable linear equalizer (402 in Fig. 4), the variable gain amplifier (404), and the line driver (406). Liao et al disclose the analog to digital converter (105 in Fig. 1; Pub [0025-0027]). Gao et al disclose the MCU (Fig. 3A and 3B; Pub [0031]). None of them explicitly teach integrated circuit.
However, Nguyen et al disclose CTLE and control range (Fig. 1 and 2). The entirety of the circuits maybe implemented in a single integrated circuit (IC) chip (Pub [0027]). An IC is well known for compact size and low cost in electronic circuit design. Therefore, it is obvious to one of ordinary skill in the art before the filling date of the claimed invention to combine the CTLE of Delshadpour et al, the ADC of Liao et al, and MCU of Gao et al with the integrated circuit (IC) chip teaching of Nguyen et al. By doing so, forms a first and second integrated circuit for different part of the receiver to optimize size, reduce cost and achieve high reliability in a communication system.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Delshadpour et al (US 11,206,161) in view of Liao et al (US 2016/0352557) (IDS), and further in view of Wang et al (US 11,444,813). a) Regarding claim 24, Delshadpour et al disclose a CTLE (402) and digital link adaptation circuitry (412 in Fig. 4). Liao et al disclose an analog to digital converter (105 in Fig. 1; Pub [0025-0027]). Delshadpour et al and Liao et al did not explicitly teach digital eye diagram and monitor.
However, Wang et al disclose adaptive CTLE based on samples from error slicers (Fig. 6). The goal is to configure the equalizer with the best settings to provide optimal equalization. An eye diagram is a graphical representation of a digital signal over multiple cycles, formed by overlaying many bit sequences to create an eye-like shape. Applying equalization widens and opens the eye, improving both the vertical and horizontal margins (Fig. 5; Col 4, L59-Col 5, L8). Therefore, it is obvious to one of ordinary skill in the art before the filling date of the claimed invention to combine the CTLE of Delshadpour et al, the ADC of Liao et al, and the eye monitor of Wang et al to output a digital eye diagram from the digital link adaptation circuitry to a digital eye monitor. By doing so, allows the receiver to sample the signal more accurately, reducing BER and increasing effective SNR.
Allowable Subject Matter
Claims 3-9, 15-19, and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 27-35 are allowed.
The following is an examiner’s statement of reasons for allowance: The present invention is directed to digital link adaptation with re-drivers. The closest prior art Delshadpour et al disclose the programmable linear equalizer (402 in Fig. 4), the variable gain amplifier (404), and the line driver (406). Liao et al disclose the analog to digital converter (105 in Fig. 1; Pub [0025-0027]). Gao et al disclose the MCU (Fig. 3A and 3B; Pub [0031]). However, none of the prior art teach or suggest sampling, at an extension device, an analog signal transmitted by a transmitter via a channel using an analog-to-digital converter, where the transmitted analog signal is a pulse; characterizing, at the extension device, the channel based upon the sampled analog signal; generating, at the extension device, parameters that are capable of being used by the transmitter to program an equalizer; and transmitting, by the extension device, the generated parameters to the transmitter. Further, the digital link adaptation circuitry comprising: an analog to digital converter; and a microcontroller unit (MCU); wherein the digital link adaptation circuitry is capable of: sampling the amplified signal to produce a sampled signal when the transmitted analog signal is a pulse; measuring a channel impulse response; characterizing the channel by taking the derivative of the measured channel impulse response having a duration that is greater than a time required for transients caused by reflections of the pulse within the channel to have settled; generating programming parameters for the programmable linear equalizer based upon the characterization of the channel; programming the programmable linear equalizer using the programming parameters for the programmable linear equalizer; generating programming parameters for the programmable variable gain amplifier based upon the characterization of the channel; programming the programmable variable gain amplifier using the programming parameters for the programmable variable gain amplifier; generating programming parameters for a transmitter that are capable of being used by the transmitter to program a plurality of taps of a feed forward equalizer based upon the characterization of the channel; and transmitting the programming parameters for the transmitter to the transmitter; wherein the programmable linear equalizer, the variable gain amplifier, and the line driver are formed on a first integrated circuit; wherein at least one of the analog to digital converter and the MCU are formed on a second integrated circuit capable of receiving signals from the first integrated circuit; and wherein the MCU is configured to receive a clock signal from a crystal oscillator (emphasis added).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 8,619,848 Jiang disclose compensate ISI interference.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eva Y Puente whose telephone number is 571-272-3049. The examiner can normally be reached on M-F, 7:30 AM to 5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh Fan can be reached on 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
July 9, 2026
/EVA Y PUENTE/ Primary Examiner, Art Unit 2632
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