CTFR 19/082,123 CTFR 90348 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-3 and 5-10 are currently pending and prosecuted . Information Disclosure Statement The information disclosure statement (IDS) submitted on 6 April 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Response to Arguments Applicant’s arguments with respect to claims 1-3 and 5-9 have been considered but are moot because the new ground of rejection is necessitated due to Applicant’s amendments. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-3 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al., U SPG-Pub 2021/0202676 , hereinafter Jeong, in view of Kim et al., US PG-Pub 2022/0206616 , hereinafter Kim, utilizing Foreign Application Priority Date of 30 December 2020 . Regarding Claim 1 , Jeong teaches an electronic device ( display apparatus ), comprising: a first diode ( light emitting device ED of first subpixel SP1; Fig. 8 , and corresponding descriptions); a first transistor ( driving TFT Tdr of first subpixel SP1; Fig. 8 , and corresponding descriptions) coupled to the first diode ( Fig. 8 , and corresponding descriptions ; [0261]-[0265] ) and comprising a semiconductor ( [0261], “the driving TFT Tdr may be a TFT including a semiconductor layer (or an active layer)” ); a second transistor ( first switching transistor Tsw1 of first subpixel SP1; Fig. 8 , and corresponding descriptions) coupled to the first transistor ( Fig. 8 , and corresponding descriptions ; [0261]-[0265] ); a second diode ( light emitting device ED of third subpixel SP3; Fig. 8 , and corresponding descriptions); a third transistor ( driving TFT Tdr of third subpixel SP3; Fig. 8 , and corresponding descriptions) coupled to the second diode ( Fig. 8 , and corresponding descriptions ; [0261]-[0265] ) and comprising a semiconductor ( [0261], “the driving TFT Tdr may be a TFT including a semiconductor layer (or an active layer)” ); a fourth transistor ( first switching transistor Tsw1 of third subpixel SP3; Fig. 8 , and corresponding descriptions) coupled to the third transistor ( Fig. 8 , and corresponding descriptions ; [0261]-[0265] ); a signal line ( gate line Glo to GLe ) coupled to the second transistor and the fourth transistor ( Fig. 8 , and corresponding descriptions ; [0261]-[0265] ); a data line ( data line DLo to DLe ) coupled to the second transistor ( Fig. 8 , and corresponding descriptions, showing the data line DL is connected to the first switching transistor in each subpixel ; [0261]-[0265] ), and a power line ( power sharing line PSL ) coupled to the first transistor and the third transistor ( Fig. 8 , and corresponding descriptions, showing the power sharing line PSL is coupled to the driving transistors ; [0261]-[0265] ), wherein the power line is disposed between the semiconductor of the first transistor and the semiconductor of the third transistor ( Fig. 8 , and corresponding descriptions, showing the power sharing line PSL is located between the driving TFT Tdr of each subpixel). However, Jeong does not explicitly teach wherein in a top view direction, the data line at least partially overlaps the semiconductor of the first transistor Kim teaches wherein in a top view direction, the data line at least partially overlaps the semiconductor of the first transistor ( Kim: Fig. 3 , and corresponding descriptions, showing how the data lines D1-DLm overlap a portion of the semiconductor of the driving transistor M1a-M1d in a plan view). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the invention to incorporate the circuit layout taught by Kim into the device taught by Jeong in order to accurately receive the data line signal ( Kim: [0050] ), thereby providing a higher quality display device. Regarding Claim 2 , Jeong, as modified by Kim, teaches the electronic device as claimed in claim 1, wherein the data line and the power line extend along a same direction ( Jeong: Fig. 8 , and corresponding descriptions, showing the data line and the power line extend along the same direction for a portion of the circuit). Regarding Claim 3 , Jeong, as modified by Kim, teaches the electronic device as claimed in claim 2. However, Jeong does not explicitly teach wherein a maximum width of the power line is greater than a maximum width of the data line. It would have been an obvious matter of design choice to change the width of the various wires, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose , 105 USPQ 237 (CCPA 1955). Regarding Claim 5 , Jeong, as modified by Kim, teaches the electronic device as claimed in claim 1, wherein the second transistor and the fourth transistor are respectively disposed on two opposite sides of the power line ( Jeong: Fig. 8 , and corresponding descriptions, showing the switching transistors are on opposite sides of the power sharing line). Regarding Claim 6 , Jeong, as modified by Kim, teaches the electronic device as claimed in claim 5, wherein the signal line crosses the power line ( Jeong: Fig. 8 , and corresponding descriptions, showing the gate line crosses the power sharing line). Regarding Claim 7 , Jeong, as modified by Kim, teaches the electronic device as claimed in claim 5, wherein the signal line is used as a gate of the second transistor and a gate of the fourth transistor Jeong: ( Fig. 8 , and corresponding descriptions ; [0262], “The first switching TFT Tsw1 may include a gate electrode connected to the adjacent gate lines GLo and GLe” ). Regarding Claim 8 , Jeong, as modified by Kim, teaches the electronic device as claimed in claim 1, wherein the power line comprises a main portion ( Jeong: power line PL ) extending along a direction ( Jeong: Fig. 8 , and corresponding descriptions, showing the power line extends along a vertical direction) and two extension portions ( Jeong: power sharing lines PSL ) respectively overlapped with the semiconductor of the first transistor and the semiconductor of the third transistor ( Jeong: Figs. 6 and 8 , and corresponding descriptions, showing the power sharing line overlaps the driving transistors). Regarding Claim 9 , Jeong, as modified by Kim, teaches the electronic device as claimed in claim 8, wherein the two extension portions respectively extending along two directions different from the direction ( Jeong: Figs. 6 and 8 , and corresponding descriptions, showing the power sharing lines extend in a horizontal direction, which is different from a vertical direction). Regarding Claim 10 , Jeong, as modified by Kim, teaches the electronic device as claimed in claim 1, further comprising an insulating layer ( Jeong: insulation layer 101c ) disposed between the semiconductor of the first transistor and the data line ( Jeong: Figs. 6, 15-16 and 20 , and corresponding descriptions ; [0662] ), wherein the data line is coupled to a semiconductor of the second transistor through a through hole of the insulating layer ( Jeong: Figs. 6, 15-16 and 20 , and corresponding descriptions ; [0662], “The contact line CPLc may be electrically connected to the second pixel common power line CPLb through a contact hole disposed in the interlayer insulation layer 101 c and may be electrically connected to the first pixel common power line CPLa through a contact hole disposed in the interlayer insulation layer 101 c and a buffer layer 101 a .” ). Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN T REED whose telephone number is (571)272-7234. The examiner can normally be reached M-F: 0800-1800. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. STEPHEN T. REED Primary Examiner Art Unit 2627 /Stephen T. Reed/Primary Examiner, Art Unit 2627 Application/Control Number: 19/082,123 Page 2 Art Unit: 2627 Application/Control Number: 19/082,123 Page 3 Art Unit: 2627 Application/Control Number: 19/082,123 Page 4 Art Unit: 2627 Application/Control Number: 19/082,123 Page 5 Art Unit: 2627 Application/Control Number: 19/082,123 Page 6 Art Unit: 2627 Application/Control Number: 19/082,123 Page 7 Art Unit: 2627
Prosecution Insights