DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (pub # 20240355281) in view of Kim et al (pub # 20240221618).
Consider claim 1. Jang et al teaches A light-emitting device, (paragraph 0080, The display device 10 may be a light emitting display device). comprising:
a first power supply pad, configured to receive a first power voltage; (Fig. 11 and paragraph 0297, a first power pad VDPD).
a second power supply pad, configured to receive a second power voltage; (Fig. 11 and paragraph 0297, a second power pad VSPD).
a plurality of driving pads, configured to receive driving signals; (Fig. 11 and paragraph 0297, gate driving control pads GCPD).
a plurality of data pads, configured to receive data signals; (Fig. 11 and paragraph 0297, data pads DTPD).
and a plurality of pixels, (Fig. 1 and paragraph 0083, unit pixels UPX. Also see Fig. 5 which discloses the pixel driving circuit PXD for each pixel).
each pixel comprising:
a first power supply terminal (Fig. 5 and paragraph 0133, and a first power line VDL that transmits the first power ELVDD to the pixel drivers PXD
formed on a silicon substrate (paragraph 0107, The circuit layer 120 further may include a first power supply line VDSPL (see FIG. 9). Paragraph 0227, the circuit layer 120 may include a buffer layer 121 disposed on the substrate 110. Paragraph 0228, each of the buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124 may be formed of multiple layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer may be alternately stacked each other, thus the circuit layer 120 is a silicon substrate).
and coupled to the first power supply pad, configured to receive the first power voltage; (paragraph 0297, a first power pad VDPD for transmitting the first power ELVDD).
a second power supply terminal formed on the silicon substrate and coupled to the second power supply pad, configured to receive the second power voltage; (Fig. 5 and paragraph 0108, the second power supply line VSSPL respectively transmit a first power ELVDD (see FIG. 5) and a second power ELVSS (scc FIG. 5). Paragraph 0297, a second power pad VSPD for transmitting the second power ELVSS).
a driving terminal formed on the silicon substrate and coupled to a driving pad, configured to receive a driving signal; (Fig. 5 and paragraph 0135, a gate control line GCL that transmits a gate control signal GC to the pixel driver PXD. Paragraph 0297, gate driving control pads GCPD for transmitting gate driving control signals).
a data terminal formed on the silicon substrate and coupled to a data pad, configured to receive a data signal; (Fig. 5 and paragraph 0133, the data line DL that transmits the data signal Vdata to the pixel drivers PXD. Paragraph 0297, data pads DTPD for transmitting the data signals Vdata).
a plurality of light-emitting diodes (LEDs) formed on the silicon substrate; (paragraph 0215, the light emitting element layer 130 on the circuit layer 120. Paragraph 0110, The light emitting element layer 130 may include light emitting elements LEL (scc FIG. 5) respectively corresponding to the emission areas EA).
and a control circuit formed on the silicon substrate, (Fig. 5 and paragraph 0106, The circuit layer 120 may include pixel driver PXD).
coupled to the first power supply terminal, (Fig. 5, PXD connected to first power ELVDD).
the second power supply terminal, (Fig. 5, PXD connected to second power ELVSS)
the driving terminal, (Fig. 5 and paragraph 0133, gate lines GL (GWL, GIL, ECL, and GCL) that transmit the gate signals GW, GI, EM, and GC to the pixel drivers PXD).
the data terminal and the plurality of LEDs, (Fig. 5 and paragraph 0133, the data line DL that transmits the data signal Vdata to the pixel drivers PXD).
and configured to control operations of the plurality of LEDs based on the received driving signal and the received data signal. (See at least paragraph 0136, One pixel driver PXD among the pixel drivers PXD of the circuit layer 120 may include a driving transistor DT generating a driving current to drive the light emitting element LEL electrically connected to the one pixel driver PXD).
Jang et al does not specifically disclose wherein the plurality of LEDs comprises a first color LED and a second color LED, an anode of the first color LED is coupled to the first power supply terminal to receive the first power voltage, and an anode of the second color LED is coupled to the driving terminal to receive a third power voltage higher than the first power voltage.
In an analogous art Kim et al teaches wherein the plurality of LEDs comprises a first color LED and a second color LED, (Fig. 7 and paragraph 0104, first micro-LED uLED_R and second micro-LED uLED_G).
an anode of the first color LED is coupled to the first power supply terminal to receive the first power voltage, (Fig. 7 and paragraph 0106, he cathode electrode of the first micro-LED uLED_R is connected to the drain electrode of the driving transistor DR-TFT, and the anode electrode thereof is connected to the first high-potential power line EVDD_R.).
and an anode of the second color LED is coupled to the driving terminal to receive a third power voltage higher than the first power voltage; (Fig. 7 and paragraph 0107, The cathode electrode of the second micro-LED uLED_G is connected to the drain electrode of the driving transistor DR-TFT, and the anode electrode thereof is connected to the second high-potential power line EVDD_G. Paragraph 0109, The low-potential voltage EVSS or the high-potential voltage EVDD may be applied to the first high-potential power line EVDD_R to the third high-potential power line EVDD_B. Paragraph 0111, when the display device allows the second micro-LED uLED_G to emit light, the high-potential voltage EVDD may be applied to the second high-potential power line EVDD_G, while the low-potential voltage EVSS may be applied to the first high-potential power line EVDD_R and the third high-potential power line EVDD_B, thus the power voltage applied to the the second micro-LED uLED_G is higher than the power voltage applied to the first micro-LED uLED_R.).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the features of Kim et al with the invention of Jang et al so that the area size of the transmissive area of the transparent display panel may be increased, and thus the transparency thereof may be improved (Kim et al paragraph 0121).
Claim(s) 2, 4, 7, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (pub # 20240355281) in view of Kim et al (pub # 20240221618) as applied to claim 1 above, and further in view of Jeon et al (pub # 20240194127).
Consider claim 2. Jang et al in view of Kim et al does not specifically disclose The light-emitting device of claim 1, wherein the control circuit comprises:a timing control (TCON) circuit formed on the silicon substrate and coupled to the driving terminal and the data terminal, configured to provide a timing signal based on the received driving signal and the received data signal; and a pulse width modulation (PWM) control circuit formed on the silicon substrate and coupled to the timing control circuit, configured to provide PWM control signals based on the timing signal; wherein the PWM control signals are used to modulate duty cycles of currents passing through the LEDs.
However in an analogous art Jeon et al teaches a timing control (TCON) circuit formed on the silicon substrate and coupled to the driving terminal and the data terminal, (Fig. 4 and paragraph 0109, timing control circuit 600 connected to scan-driving unit 110 and data-driving circuit 300G).
configured to provide a timing signal based on the received driving signal and the received data signal; (paragraph 0109, The timing control circuit 600 receives digital video data DATA and timing signals TSS. The timing control circuit 600 may generate the first scan-driving control signal GDCS1, a second scan-driving control signal GDCS2, the first light emission control signal ECS1, the second light emission control signal ECS2, and a sweep control signal SWCS for controlling the operation timing of the scan-driving circuit 110 according to the timing signals TSS. Also, the timing control circuit 600 may generate a source control signal DCS for controlling the operation timing of the data-driving circuit 300G).
and a pulse width modulation (PWM) control circuit formed on the silicon substrate and coupled to the timing control circuit, configured to provide PWM control signals based on the timing signal; (paragraph 0118, the first pixel-driving circuit PDU1 may be a pulse width modulation PWM circuit for performing pulse width modulation of the first driving current flowing through the light-emitting element EL).
wherein the PWM control signals are used to modulate duty cycles of currents passing through the LEDs. (paragraph 0118, the first pixel-driving circuit PDU1 may be a pulse width modulation PWM circuit for performing pulse width modulation of the first driving current flowing through the light-emitting element EL).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the features of Jeon et al with the invention of Jang et al in view of Kim et al in order to reduce or minimize the effect of a voltage variation of one PWM data line on the voltage of a PWM data line adjacent thereto by an adjacent capacitance by reducing or minimizing the voltage difference between a black grayscale voltage and a global power supply voltage (Jeon et al paragraph 0028).
Consider claim 4. Jeon et al further teaches The light-emitting device of claim 2, wherein the control circuit further comprises a current driving circuit configured to modulate the duty cycles of the currents passing through the LEDs based on the PWM control signals. (paragraph 0118, the first pixel-driving circuit PDU1 may be a pulse width modulation PWM circuit for performing pulse width modulation of the first driving current flowing through the light-emitting element EL).
Consider claim 7. Jang et al in view of Kim et al does not specifically disclose The light-emitting device of claim 1, further comprising an external timing control (TCON) driver coupled to the plurality of driving pads and the plurality of data pads, and configured to generate the driving signals and the data signals.
However in an analogous art Jeon et al teaches an external timing control (TCON) driver coupled to the plurality of driving pads and the plurality of data pads, and configured to generate the driving signals and the data signals. (Fig. 4 and paragraph 0109, timing control circuit 600 connected to scan-driving unit 110 and data-driving circuit 300G. Paragraph 0109, The timing control circuit 600 receives digital video data DATA and timing signals TSS. The timing control circuit 600 may generate the first scan-driving control signal GDCS1, a second scan-driving control signal GDCS2, the first light emission control signal ECS1, the second light emission control signal ECS2, and a sweep control signal SWCS for controlling the operation timing of the scan-driving circuit 110 according to the timing signals TSS. Also, the timing control circuit 600 may generate a source control signal DCS for controlling the operation timing of the data-driving circuit 300G).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the features of Jeon et al with the invention of Jang et al in view of Kim et al in order to reduce or minimize the effect of a voltage variation of one PWM data line on the voltage of a PWM data line adjacent thereto by an adjacent capacitance by reducing or minimizing the voltage difference between a black grayscale voltage and a global power supply voltage (Jeon et al paragraph 0028).
Consider claim 9. Jang et al in view of Kim et al does not specifically disclose A method of manufacturing a plurality of light-emitting devices as claimed in claim 1, the method comprising performing wafer-level processing to simultaneously form the plurality of light-emitting devices on a single silicon wafer. However Jeon et al in at least paragraph 0276 discloses the light-emitting elements LE may be formed by being grown on a semiconductor substrate, such as a silicon wafer. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the features of Jeon et al with the invention of Jang et al in view of Kim et al in order to provide a cost effective method of fabricating and manufacturing the light-emitting devices.
Consider claim 10. Jang et al in view of Kim et al does not specifically disclose A method for efficient mass production of light-emitting devices as claimed in claim 1, the method comprising: performing wafer-level processing to simultaneously fabricate a plurality of light-emitting devices on a single silicon wafer, thereby achieving parallel fabrication of power supply pads, driving pads, data pads, pixels, LEDs, and control circuits of the plurality of light-emitting devices. However Jeon et al in at least paragraph 0276 discloses the light-emitting elements LE may be formed by being grown on a semiconductor substrate, such as a silicon wafer. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the features of Jeon et al with the invention of Jang et al in view of Kim et al in order to provide a cost effective method of fabricating and manufacturing the light-emitting devices.
Claim(s) 5, 6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (pub # 20240355281) in view of Kim et al (pub # 20240221618) as applied to claim 1 above, and further in view of Kim et al (pub # 20040080471), hereinafter referred to as D1.
Consider claim 5. Jang et al in view of Kim et al does not specifically disclose The light-emitting device of claim 1, wherein the control circuit is configured to drive the plurality of LEDs using a current sink configuration. However D1 in at least paragraph 0051 and Fig. 6 discloses a data driver 46 may include a plurality of current sink data drive IC's 52a, 52b, 52c, . . . , which may be interconnected in a cascade circuit configuration. Each of the current sink data drive IC's 52a, 52b, 52c, . . . may include a reference current supply/path part 54a and a current sink data drive IC 54b that may be driven by a reference current from the reference current supply/path part 54a. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the features of D1with the invention of Jang et al in view of Kim et al in order to provide a data-driving apparatus and method of an electro luminescence display panel that reduces output deviations between data drive IC's (D1paragraph 0016).
Consider claim 6. Jang et al in view of Kim et al does not specifically disclose The light-emitting device of claim 1, wherein the control circuit is configured to drive the plurality of LEDs using a current source configuration. However D1in at least paragraph 0070 discloses a data driver 66 may include a plurality of current source data drive IC's 72a, 72b, 72c, . . . , which may be interconnected in a cascade circuit configuration. Each of the current source data drive IC's 72a, 72b, 72c, . . . may include a reference current supply/path part 74a and a current source data drive IC 74b that may be driven by a reference current from the reference current supply/path part 74a. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the features of D1with the invention of Jang et al in view of Kim et al in order to provide a data-driving apparatus and method of an electro luminescence display panel that reduces output deviations between data drive IC's (D1 paragraph 0016).
Consider claim 8. Jang et al in view of Kim et al does not specifically disclose The light-emitting device of claim 1, further comprising a plurality of cascaded timing control (TCON) drivers coupled to the plurality of driving pads and the plurality of data pads, and configured to generate the driving signals and the data signals. However D1in at least paragraph 0051 and Fig. 6 discloses a data driver 46 may include a plurality of current sink data drive IC's 52a, 52b, 52c, . . . , which may be interconnected in a cascade circuit configuration. Each of the current sink data drive IC's 52a, 52b, 52c, . . . may include a reference current supply/path part 54a and a current sink data drive IC 54b that may be driven by a reference current from the reference current supply/path part 54a. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the features of D1with the invention of Jang et al in view of Kim et al in order to provide a data-driving apparatus and method of an electro luminescence display panel that reduces output deviations between data drive IC's (D1 paragraph 0016).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (pub # 20240355281) in view of Kim et al (pub # 20240221618) and further in view of Jeon et al (pub # 20240194127) and further in view of Jung et al (pub # 20240212612).
Consider claim 3. Jang et al in view of Kim et al and further in view of Jeon et al does not specifically disclose The light-emitting device of claim 2, wherein the control circuit further comprises an identification setting unit configured to setting the identification of the each pixel based on the received driving signal. However Jung et al in at least paragraph 0019 discloses a drive IC that receives control data packets wherein the control data packet can include an identification code indicating that pixel data to be written to the one pixel line is data in one of the high-speed driving area or data in the low-speed driving area. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the features of Jung et al with the invention of Jang et al in view of Kim et al and further in view of Jeon et al in order to provide an efficient and accurate method of driving the display of the pixels.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAYCE R BIBBEE whose telephone number is (571)270-7222. The examiner can normally be reached Mon-Thurs 8:00-6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHAYCE R BIBBEE/Examiner, Art Unit 2624
/MATTHEW A EASON/Supervisory Patent Examiner, Art Unit 2624
Prosecution Insights