DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Species I: [figures 1-4, corresponding to claims 25-30 & 37-41] in the reply filed on 2/12/2026 is acknowledged. The traversal is on the ground(s) that “Neither Applicant nor the Patent and Trademark Office should be put through the trouble and expense entailed in multiple filing and prosecution. Further, the making of an election-of-species requirement is not mandatory in all instances. It is submitted that it would not be an undue burden on the Examiner to examine all of the pending claims in the present application.” [Remarks: pg. 2, 2nd para.]. This is not found persuasive because the different species would require different search strategies and search areas. For example, each Species VI – XIV would require additional search strategies and search areas corresponding to the different electronic device configurations. Species III-V corresponds to manufacturing of semiconductor devices, which corresponds to a different search area requiring different search strategies.
Claims 31-36 & 42-48 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 2/12/2026.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/18/2025, 4/2/2025, 5/19/2025, 8/6/2025, & 1/15/2026 are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 25, 37, & 40-41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kreye et al. (US 20130099700), in view of Peng et al. (US 20190371244).
As to claim 25, Kreye teaches a light emitting apparatus [abstract & fig. 2] in which a pixel [figs. 1-2 & 10 & para. 45 & 48-50], that comprises a current path including (1) a light emitting element [figs. 1-2 & 10 & para. 45 & 48-50], (2) a driving transistor (low-volt PMOS transistor Mdrive 1) [fig. 10 & para. 53] configured to supply a current corresponding to a luminance signal to the light emitting element, and (3) a light emission control transistor (medium-volt or high-volt PMOS transistor Mmv 4) [fig. 10 & para. 53] configured to control light emission or non-light emission of the light emitting element [fig. 10] by a light emission control signal (vss) [] supplied to a gate electrode, is arranged,
wherein in the current path, the light emission control transistor is arranged between the light emitting element and the driving transistor [fig. 10 & para. 53], and
wherein a withstand voltage (drive transistor utilizing low-volt PMOS transistor Mdrive 1 & light emission control transistor utilizing medium-volt or high-volt PMOS transistor Mmv 4) [fig. 10 & para. 53] of the driving transistor is lower than a withstand voltage of the light emission control transistor.
Kreye does not explicitly teach wherein the light emission control transistor is in an off-state during a non-light emission period.
Peng teaches the concept of a light emitting apparatus [abstract], wherein a light emission control transistor (bridge transistor 802) [figs. 8 & para. 42-44] is in an off-state during a non-light emission period (when light emitting element 804 is turned-off, bridge transistor 802 is turned-off) [para. 43].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the light emission control transistor of the light emitting apparatus of Kreye, such that the light emission control transistor is in an off-state during a non-light emission period, as taught by Peng, to reduce power consumption and improve image quality by reducing parasitic losses, as one of ordinary skill in the art would appreciate.
As to claim 37, Kreye as modified by Peng teaches the apparatus according to claim 25, further comprising a signal output circuit (vdrive corresponding to vsenseout) [Kreye: figs. 6 & 10 & para. 56] configured to supply the luminance signal to a control terminal of the driving transistor (low-volt PMOS transistor Mdrive 1 controlled via Vdrive) [Kreye: fig. 10 & para. 53],
wherein a withstand voltage of a transistor arranged in the signal output circuit is lower than the withstand voltage of the light emission control transistor (storage circuit 10 & sense amplifier 20 comprise only low-volt transistors) [Kreye: para. 53].
As to claim 40, Kreye as modified by Peng teaches the apparatus according to claim 25, wherein the withstand voltage of the light emission control transistor is the highest among the transistors included in the apparatus [Kreye: para. 53 & 28].
As to claim 41, Kreye as modified by Peng teaches the apparatus according to claim 25, wherein the apparatus comprises a substrate (substrate) [Kreye: figs. 1-2 & para. 23 & 45] and a plurality of pixels including the pixel on the substrate [figs. 1-2 & 10 & para. 45 & 48-50], and
wherein the plurality of pixels are arranged along a longitudinal direction of the substrate [Kreye: figs. 1-2 & para. 23 & 45].
Claim(s) 29-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kreye, in view of Peng, and further in view of You (US 20100102386).
As to claim 29, Kreye as modified by Peng teaches the apparatus according to claim 25 (see above).
Kreye as modified by Peng does not explicitly teach wherein the light emission control transistor comprises a drain offset structure.
You teaches the concept of a transistor [abstract & fig. 7] that comprises a drain offset structure (note drain is offset from gate) [fig. 7 & para. 55 & 37].
Because Kreye, Peng, and You are in the same field of endeavor, i.e., semiconductor transistors utilized with electronic devices, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to simply substitute the light emission control transistor of the pixel of the light emitting apparatus of Kreye as modified by Peng, with a light emission control transistor comprises a drain offset structure, as taught by You, for the purposes of achieving the predictable result of controlling current flow through the transistor.
As to claim 30, Kreye as modified by Peng teaches the apparatus according to claim 25 (see above).
Kreye as modified by Peng does not explicitly teach wherein the light emission control transistor comprises a LOCOS offset structure.
You teaches the concept of a transistor [abstract & fig. 7] that comprises a LOCOS offset structure (note drain is offset from gate & locos hv drain oxide 616) [fig. 7 & para. 55 & 37].
Because Kreye, Peng, and You are in the same field of endeavor, i.e., semiconductor transistors utilized with electronic devices, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to simply substitute the light emission control transistor of the pixel of the light emitting apparatus of Kreye as modified by Peng, with a light emission control transistor comprises a LOCOS offset structure, as taught by You, for the purposes of achieving the predictable result of controlling current flow through the transistor.
Allowable Subject Matter
Claims 26-28 & 38-39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhou et al. (US 20180166011).
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/DAVID TUNG/Primary Examiner, Art Unit 2622