Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed 03/18/2025 fails to comply with 37 CFR 1.98(a)(1), which requires the following: (1) a list of all patents, publications, applications, or other information submitted for consideration by the Office; (2) U.S. patents and U.S. patent application publications listed in a section separately from citations of other documents; (3) the application number of the application in which the information disclosure statement is being submitted on each page of the list; (4) a column that provides a blank space next to each document to be considered, for the examiner’s initials; and (5) a heading that clearly indicates that the list is an information disclosure statement. The information disclosure statement has been placed in the application file, but the information referred to therein has not been considered.
The IDS filed 03/8/2025 does not cite any references.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 12, and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 11, and 17 of U.S. Patent No. 12,277,018 in view of Park et al., US Patent Appl. Pub. No. 2014/0157030.
Claims 1, 11, and 17 of U.S. Patent No. 12,277,018 disclose all claim limitations of respective claims 1, 12, and 21 in the current Application except controlling, by the memory controller, the memory system to maintain in the transition mode for a first period of time.
Park teaches sequentially transitioning a main memory device 1500 (FIG. 1) from Normal Mode 110 into Idle Mode 120, followed by a Sleep Mode 130 (the Idle and Sleep mode forming a transition mode – FIG(s) 1 and 5, paragraph 0094). Park further teaches maintaining the main memory device in the Idle Mode, which is part of the transition mode, based on a predetermined idle time duration (i.e. first period of time – paragraph 0094, lines 11-13). Thus, reducing the power consumption (paragraphs 0005-0007).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the above-described memory device an functionality, as suggested by Park with claims 1, 11, and 17 of U.S. Patent No. 12,277,018 in order to implement controlling, by the memory controller, the memory system to maintain in the transition mode for a first period of time. One of ordinary skill in the art would be motivated to do so in order to reduce the power consumption.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10, 12, 18 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al., US Patent Appl. Pub. No. 2014/0157030.
Regarding claim 1, Park discloses a memory system (FIG(s) 1 and 5), comprising:
at least one memory device (FIG. 1, main memory device 1500); and
a memory controller (not shown) coupled with the at least one memory device and configured to (FIG. 1, paragraph 0068, lines 6-10):
control the memory system to enter a first activation mode (FIG. 5, entering Normal mode 110 from either the Idla Mode 110 or the Sleep Mode 130 – paragraph 0094, lines 21-26) and a transition mode sequentially (the transition mode includes the Idle Mode 120 plus the Sleep Mode 130, which are entered sequentially – FIG. 5, paragraph 0094, lines 8-13); and
control the memory system to maintain in the transition mode for a first period of time (the main memory device remains in the Idle Mode, which is part of the transition mode, based on a predetermined idle time duration – i.e. first period of time, paragraph 0094, lines 11-13); wherein:
the transition mode includes an idle mode and a first sleep mode (the transition mode includes the Idle Mode 120 plus the Sleep Mode 130 – FIG. 5, paragraph 0094, lines 8-13), a power of the memory system in the first sleep mode is less than a power of the memory system in the idle mode (paragraphs 0099-0100), and
the power of the memory system in the idle mode is less than a power of the memory system in the first activation mode (paragraphs 0098-0099).
Regarding claim 12, Park discloses a method with all claim limitations, as addressed above for claim 1.
Regarding claim 18, Park discloses a memory controller, comprising:
a memory (FIG. 1, main memory 1500); and
a circuit configured (external device/circuit [not shown], generating respective signals for controlling the operational modes – paragraph 0094, lines 1-5) to:
control a memory system including the memory controller (memory system formed by the memory controller [not shown] and the main memory 1500 – FIG. 1, paragraph 0068, lines 6-10) to enter a first activation mode (FIG. 5, entering Normal mode 110 from either the Idla Mode 110 or the Sleep Mode 130 – paragraph 0094, lines 21-26) and a transition mode sequentially (the transition mode includes the Idle Mode 120 plus the Sleep Mode 130, which are entered sequentially – FIG. 5, paragraph 0094, lines 8-13); and
control the memory system to maintain in the transition mode for a first period of time (the main memory device remains in the Idle Mode, which is part of the transition mode, based on a predetermined idle time duration – i.e. first period of time, paragraph 0094, lines 11-13); wherein:
the transition mode includes an idle mode and a first sleep mode (the transition mode includes the Idle Mode 120 plus the Sleep Mode 130 – FIG. 5, paragraph 0094, lines 8-13),
a power of the memory system in the first sleep mode is less than a power of the memory system in the idle mode (paragraphs 0099-0100), and
the power of the memory system in the idle mode is less than a power of the memory system in the first activation mode (paragraphs 0098-0099).
Regarding claim 21, Park discloses a non-transitory medium containing computer-executable instructions that, when executed by a hardware controller of an electrical device (memory controller executing firmware – paragraph 0068, lines 6-10), cause the hardware controller to perform a method of operating the electrical device, the method comprising:
controlling, the electrical device to enter a first activation mode (FIG. 5, entering Normal mode 110 from either the Idla Mode 110 or the Sleep Mode 130 – paragraph 0094, lines 21-26) and a transition mode sequentially (the transition mode includes the Idle Mode 120 plus the Sleep Mode 130, which are entered sequentially – FIG. 5, paragraph 0094, lines 8-13); and
controlling the electrical device to maintain in the transition mode for a first period of time (the main memory device remains in the Idle Mode, which is part of the transition mode, based on a predetermined idle time duration – i.e. first period of time, paragraph 0094, lines 11-13), wherein:
the transition mode includes an idle mode and a first sleep mode (the transition mode includes the Idle Mode 120 plus the Sleep Mode 130 – FIG. 5, paragraph 0094, lines 8-13),
a power of the electrical device in the first sleep mode is less than a power of the electrical device in the idle mode (paragraphs 0099-0100), and
the power of the electrical device in the idle mode is less than a power of the electrical device in the first activation mode(paragraphs 0098-0099).
Regarding claim 10, Park further teaches the memory system, further comprising: a power management module FIG. 1, PMIC 1700) configured to control a power supply of the memory system to realize switching of working modes of the memory system, the working modes including the first activation mode and the transition mode (paragraph 0070).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al., US Patent Appl. Pub. No. 2014/0157030.
Regarding claims 4 and 20, Park discloses the system and controller as per claims 1 and 18, respectively.
Park does not specifically state the duration of the memory system in the first sleep mode is longer than a duration of the memory system in the idle mode.
However, Park clearly teaches that the power consumption during the Idle Mode 120 is less that the power consumption during the Sleep Mode 130 (FIG. 5, paragraphs 0099-0100). In view of these teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to extend the duration of the Sleep Mode relative to the duration of the Idle Mode. One of ordinary skill in the art would be motivated to do so in order to achieve a higher reduction in the overall power consumption.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al., US Patent Appl. Pub. No. 2014/0157030 in view of “Universal Flash Storage” (referred to as NPL1 hereafter).
Regarding claim 11, Park discloses the system as per claim 1. In addition, Park further discloses a portion of the main memory device system (i.e. a portion of the memory system) being a non-volatile memory (FIG. 1, 1520) used for store data from the volatile memory 1520 prior of powerdown (paragraph 0067, lines 7-9, paragraph 0068, lines 1-6).
Park does not specifically state the non-volatile memory being Universal Flash Storage – i.e. the memory system comprises a Universal Flash Storage apparatus.
NPL1 teaches utilizing Universal Flash Storage to achieve higher data transfer speed and increased reliability flash memory storage, while preventing the need for different adapters for different types of flash cards (NPL1, page 1, Universal Flash Storage (UFS) section).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the UFS as suggested by NPL1 with the memory system disclosed by Park in order to implement the memory system comprises a Universal Flash Storage apparatus. One of ordinary skill in the art would be motivated to do so in order to achieve higher data transfer speed and increased reliability flash memory storage, while preventing the need for different adapters for different types of flash cards.
Allowable Subject Matter
Claims 2-3, 5-9, 13-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 2, 13 and 19, Park discloses a second sleep mode (FIG. 5, Maximum Sleep Mode 140. However, Park does not disclose controlling the memory system to automatically enter a second activation mode and a second sleep mode sequentially after maintaining the transition mode for the first period of time, wherein a power of the memory system in the second sleep mode is less than a power of the memory system in the second activation mode, as required by claims 2, 13 and 19.
Regarding claim 3, Park discloses both an idle mode and a first sleep mode (FIG. 5, Idle Mode 120 and Sleep mode 130, respectively). However, Park does not disclose the ratio between a duration of the memory system in the idle mode and a duration of the memory system in the first sleep mode being determined based on historical data of the memory system switching from the idle mode to the first activation mode, as required by claim 3.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEFAN STOYNOV whose telephone number is (571)272-4236. The examiner can normally be reached 8AM - 4:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEFAN STOYNOV/Primary Examiner, Art Unit 2175
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