DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 2 of U.S. Patent No. 12,272,702. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are teaching a substrate with a first and second pixel group arranged in three rows and three columns, first to nine transfer transistors comprising a gate and a floating diffusion, a selection transistor in at least one of the fourth to sixth pixels in each of the groups, source follower transistors respectively disposed in at least two pixels of the first to third pixels and the seventh to ninth pixels in each of the first and second pixel groups; and a dummy transistor, which is disposed in at least one pixel of the first to third pixels and the seventh to ninth pixels in each of the first and second pixel groups, wherein source follower gates of the source follower transistors are connected to each other and the floating diffusion region of each of the first to ninth transfer transistors.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2018/0343404 ("Hwang") in view of U.S. Patent Publication No. 2020/0321367 ("Kobayashi") further in view of U.S. Patent Publication No. 2017/0171488 ("Oike") further in view of U.S. Patent Publication No. 2010/0182465 ("Okita").
Regarding claim 1, Hwang discloses an image sensor, comprising:
a substrate (inherent, Fig. 3A, see paragraph [0048] photodiodes are disposed in a substrate) including a first pixel group (SP4, Fig. 3A) and a second pixel group (SP0, Fig. 3A), which are directly adjacent to each other in a first direction (for example, vertical direction, Fig. 3A), each of the first and second pixel groups (SP4, SP0, Fig. 3A) comprising first to ninth pixels (each group has nine sub-pixels, Fig. 3A), which are arranged to form three rows in the first direction (three rows, Fig. 3A) and three columns in a second direction (three columns, Fig. 3A), the first to third pixels constituting a first column (first column has three sub-pixels, Fig. 3A), the fourth to sixth pixels constituting a second column (second column has three sub-pixels, Fig. 3A), and the seventh to ninth pixels constituting a third column (third column has three sub-pixels, Fig. 3A).
Hwang does not explicitly disclose the transistor details within the specific pixel arrangement in Fig. 3A.
However, Kobayashi discloses first to ninth transfer transistors (80, 91, Fig. 4), each of the first to ninth transfer transistors comprising a transfer gate (TG, Fig. 4, paragraph [0097]) and a floating diffusion region (FD, Fig. 4, paragraph [0097]);
a selection transistor (94, Fig. 4) disposed in at least one of the fourth to sixth pixels (all pixels, including the fourth to sixth pixels, include a selection transistor, see Fig. 4); and
source follower transistors (93, Fig. 4, paragraph [0101]) respectively disposed in at least two pixels of the first to third pixels and the seventh to ninth pixels (all pixels, including the first to third pixels and the seventh to ninth pixels, include a source follower transistor, see Fig. 4), wherein source follower gates of the source follower transistors (gate of 93, Fig. 4, see circuit in Fig. 5, paragraph [0096]) are connected to the floating diffusion region of each of the first to ninth transfer transistors (91, Fig. 4).
It would have been an obvious matter of design choice to one of ordinary skill in the art before the effective filing date to select specific sub-pixels for placement of the transfer, source follower, and select transistors, as disclosed by Kobayashi as an example, in the device of Hwang in order to optimize the space and function of the pixels.
Hwang in view of Kobayashi does not disclose a dummy transistor, which is disposed in at least one pixel of the first to third pixels and the seventh to ninth pixels in each of the first and second pixel groups, nor that the source follower transistors are connected to each other.
However, Oike discloses a dummy transistor (DMT, Fig. 17, are arranged in almost every pixel within the 4x4), which is disposed in at least one pixel of the first to third pixels (see Fig. 17, selecting a 3x3 area within the 4x4 array, there is at least one dummy pixel in the first column) and the seventh to ninth pixels in each of the first and second pixel groups (see Fig. 17, selecting a 3x3 area within the 4x4 array, there is at least one dummy pixel in the third column).
It would have been obvious to one of ordinary skill in the art before the effective filing date to add dummy transistors as disclosed by Oike in the device of Hwang in view of Kobayashi in order to hold periodicity and suppress fixed-pattern noise.
Hwang in view of Kobayashi and Oike does not disclose that the gates of the source follower transistors are connected to each other.
However, Okita discloses the gates of the source follower transistors are connected to each other (see Figs. 6A-6B).
It would have been obvious to one of ordinary skill in the art before the effective filing date to connect the source followers to each other as disclosed by Okita in the device of Hwang in view of Kobayashi and Oike in order to enable the ability to change the type of addition/binning and readout of specific pixels within a group.
Regarding claim 2, Hwang in view of Kobayashi, Oike, and Okita discloses the image sensor of claim 1, and Hwang further discloses that the ninth pixel of the first pixel group (bottom rightmost pixel in group SP4, Fig. 3A) and the seventh pixel of the second pixel group (top rightmost pixel in SP0, Fig. 3A) are adjacent to each other in the first direction (vertical direction, Fig. 3A). Further, Oike disclose that the dummy transistor comprises:
in each of the first and second pixel groups (see groups in Fig. 13), a first dummy transistor disposed in the second pixel (see Fig. 17, selecting a 3x3 group, for example, the first three rows of the second to fourth columns, within the 4x4 array, a second pixel would include a dummy transistor DMT shown in a dark shade);
a second dummy transistor disposed in the seventh pixel (top right corner pixel has DMT, Fig. 17); and
a third dummy transistor disposed in the ninth pixel (ninth pixel has a DMT, Fig. 17).
It would have been an obvious matter of design choice to one of ordinary skill in the art before the effective filing date to add dummy transistors in specific pixels as disclosed by Oike in the device of Hwang in view of Kobayashi, Oike, and Okita in order to hold periodicity and suppress fixed-pattern noise.
Regarding claim 3, Hwang in view of Kobayashi, Oike, and Okita discloses the image sensor of claim 2, and Oike further discloses that, in each of the first and second pixel groups, the second dummy transistor and the third dummy transistor are respectively arranged on an active region on the substrate (see Fig. 17), and wherein the active region in which the second dummy transistor is arranged and the active region in which the third dummy transistor is arranged have a mirror-symmetrical shape along the first direction in a planar view (see Fig. 17).
Regarding claim 4, Hwang in view of Kobayashi, Oike, and Okita discloses the image sensor of claim 1, wherein the third pixel, the sixth pixel, and the ninth pixel of the first pixel group (see last row of SP4, Fig. 3A) are respectively adjacent to the first pixel, the fourth pixel, and the seventh pixel of the second pixel group in the first direction (see top row of SP0, Fig. 3A), and in each of the first and second pixel groups, the dummy transistor is arranged in the second pixel (dummy transistor in second pixel is taught by Oike in Fig. 17), and the selection transistor comprises:
a first selection transistor (SEL, Fig. 17 of Oike) arranged in the fourth pixel of the second pixel group (see Oike, Fig. 17); and a second selection transistor arranged in the sixth pixel of the first pixel group (all pixels have a SEL, Fig. 17 of Oike), and further comprising an output line connecting a source/drain region of the first selection transistor and a source/drain region of the second selection transistor (see Fig. 17, paragraph [0203]).
Regarding claim 5, Hwang in view of Kobayashi, Oike, and Okita discloses the image sensor of claim 1, and Hwang further discloses that the ninth pixel of the first pixel group is adjacent to the ninth pixel of the second pixel group in the first direction (Fig. 3A, specific numbering of pixels is not limiting), and in each of the first and second pixel group, the dummy transistor is arranged in the ninth pixel (see Fig. 17 of Oike, dummy pixel in most pixels, including the ninth pixel).
Regarding claim 6, Hwang in view of Kobayashi, Oike, and Okita discloses the image sensor of claim 1, wherein the seventh pixel of the first pixel group is adjacent to the ninth pixel of the second pixel group in the first direction (Fig. 3A, specific numbering of pixels is not limiting), and in each of the first and second pixel group, the dummy transistor is arranged in the ninth pixel (see Fig. 17 of Oike, dummy pixel in most pixels, including the ninth pixel).
Regarding claim 7, Hwang in view of Kobayashi, Oike, and Okita discloses the image sensor of claim 1, and Oike further discloses that the dummy transistor comprises a dummy gate and source/drain regions at both sides thereof (paragraph [0199]), and a power voltage is applied to all of the dummy gate and the source/drain regions at both sides thereof (paragraph [0203]).
Allowable Subject Matter
Claims 8-19 are allowed.
The following is an examiner’s statement of reasons for allowance: The invention as claimed, specifically in combination with: a dual conversion transistor arranged in at least one of the third pixel, the sixth pixel and the ninth pixel in each of the first and second pixel groups, and forming a mirror symmetry along the first direction, is not taught or made obvious by the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA T. TABA whose telephone number is (571)272-1583. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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/MONICA T TABA/Examiner, Art Unit 2878
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