Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is responsive to the U.S. Patent Application Ser. No 19/082,854 filed 03/18/2025 to 07/12/2026.
Gerneral Remarks
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1.
b. Claims 1-8 are pending on the application.
Drawings
3. The drawings were received on 03/18/2025. These drawings are review and accepted by examiner.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 03/18/2025. The information disclosed therein was considered.
Priority
5. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
6. The disclosure is objected to because of the following informalities:
In the first paragraph of the specification, the status of the parent application No. 18/538,722 should be updated; namely, it has matured into U.S. Patent No. 12,277,980. Appropriate correction is required.
Double Patenting
7. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
8. Claims 1-8 of the instant application is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-9 of U.S. Patent No. 12,277,980 in view of Chen et al (US. 2015/0310924 A1).
All of the limitation of pending claim 1 can be found in conflicting claims 1 and 5 of US patent 12,277,980 with the exception of the additional limitation of “one of the first and second transistors is provided between the first bit line and power supply line, a gate of the one of the first and second transistors is connected to the word line.”
Chen et al discloses a ROM cell 100 (see Figure 1) including a first transistor 114 and a second transistor 116. The first transistor 114 is connected to a bit-line 104 of a ROM cell 100. A gate of the first transistor 114 is connected to a drain of the second transistor 116 and the gate of the second transistor 116 is connected to the first node 106 as a power supply (see paragraph 0011-0012, the a ROM cells and a plurality of bit-0 ROM cells….the source control circuit 112 comprising a second transistor 116 comprises an NMOS transistor). It would have been obvious to include the ROM cells including a first transistor and a second transistor, disclosed by Chen et al in the system comprising a ROM device, as instantly claimed for enable to determine to be a bit-1 ROM cell or a bit-0 ROM cell and thus as storing a 0 or a 1.
Claims 2-8 are therefore rejected under Patent in view of Chen et al for the same as claims 2-4 and 6-9.
Application. 19/082,854.
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Patent No.: US 12,277,980.
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Chen et al (US. 2015/0310924 A1).
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Chen et al (US. 2015/0310924 A1).
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9. Claims 1-8 of the instant application is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 11,881,273 in view of Chen et al (US. 2015/0310924 A1).
All of the limitation of pending claim 1 can be found in conflicting claims 1, 9 and 15 of US patent 11,881,273, with the exception of the additional limitation of “one of the first and second transistors is provided between the first bit line and power supply line, a gate of the one of the first and second transistors is connected to the word line.”
Chen et al discloses a ROM cell 100 (see Figure 1) including a first transistor 114 and a second transistor 116. The first transistor 114 is connected to a bit-line 104 of a ROM cell 100. A gate of the first transistor 114 is connected to a drain of the second transistor 116 and the gate of the second transistor 116 is connected to the first node 106 as a power supply (see paragraph 0011-0012, the a ROM cells and a plurality of bit-0 ROM cells….the source control circuit 112 comprising a second transistor 116 comprises an NMOS transistor). It would have been obvious to include the ROM cells includes a first transistor and a second transistor, disclosed by Chen et al in the system comprising a ROM device, as instantly claimed for enable to determined to be a bit-1 ROM cell or a bit-0 ROM cell and thus as storing a 0 or a 1.
Claims 2-8 are therefore rejected under Patent in view of Chen et al for the same as claims 2-8, 10-14 and 16-20.
Application. 19/082,854.
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Patent No.: US 11,881,273.
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Chen et al (US. 2015/0310924 A1).
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Chen et al (US. 2015/0310924 A1).
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Allowable Subject Matter
10. Claims 1-8 are presently rejected under obviousness double patenting but would be allowable provided that a terminal disclaimer is filed.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Singh et al (US. 11,114,175 B1) discloses system and method for providing a read only memory cell array.
Kohli et al (US. 2019/0080777 A1) discloses dua-bit ROM cell with virtual ground line and programmable metal track.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824
571-272-1876
Miner.luu@uspto.gov
Prosecution Insights