Prosecution Insights
Last updated: July 17, 2026
Application No. 19/082,940

SOLAR CELL ASSEMBLY AND PREPARATION METHOD THEREOF, BATTERY, AND PREPARATION TOOLING

Non-Final OA §103
Filed
Mar 18, 2025
Priority
Sep 20, 2022 — continuation of PCTCN2022119946
Examiner
GONZALEZ RAMOS, MAYLA
Art Unit
1721
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Contemporary Amperex Future Energy Research Institute (Shanghai) Limited
OA Round
1 (Non-Final)
54%
Grant Probability
Moderate
1-2
OA Rounds
1y 8m
Est. Remaining
68%
With Interview

Examiner Intelligence

Grants 54% of resolved cases
54%
Career Allowance Rate
356 granted / 656 resolved
-10.7% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 12m
Avg Prosecution
44 currently pending
Career history
693
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
85.4%
+45.4% vs TC avg
§102
5.0%
-35.0% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 656 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims Claim(s) 1-20 are currently pending. Claim(s) 12-20 have been withdrawn. Election/Restrictions Applicant’s election without traverse of Group I (claims 1-11) in the reply filed on 05/12/2026 is acknowledged. Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected solar cell assembly/battery (Group II, claims 12-13) and a preparation tooling (Group III, claims 14-20), there being no allowable generic or linking claim. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-7 and 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR20090129180A, Park et al. in view of KR20180051019A, Kim et al. Regarding claims 1 and 11 Park teaches a preparation method of a solar cell assembly [Figs. 2(a)-2(c) and 3(a)-3(d)], comprising: providing a substrate (10; see step S0) [Figs. 2(a) and 3(a), Page 9]; forming conductive layers (20) on the substrate (10) [Page 9, step S1], the conductive layers (20) being separated by a first trench along a preset direction [Figs. 2(a) and 1(b), Page 9]; arranging an isolation body (corresponding to mask M2 provided in step S2) on a side of the conductive layer (20) facing away from the substrate (10) (the mask M2 is placed on the substrate 10 after the lower electrode layer 20 is formed) [Figs. 2(b) and 3(c), Page 9], wherein the isolation body (M2) comprises a second separating member and a third separating member (corresponding to spacers 310 within mask M2) that are arranged side by side and are integrated or separable [Fig. 2(c), Pages 7 and 10]; and removing the isolation body (the mask M2 is removed) and separately inserting a new third separating member (corresponding to Mask M3) [Fig. 2(d) and Page 10]. PNG media_image1.png 848 766 media_image1.png Greyscale Figs. 2(a)-2(c) and 3(a)-3(d) Park teaches the step of sequentially stacking and depositing a CIGS semiconductor layer (31) and a transport layer (n-type CdS buffer layer, 32, or ZnO window layer, 33) on at least one side of the isolation body (M2) along the preset direction (See step S2) [Figs. 2(b) and 3(c), Pages 7 and 9-10], the method further comprising depositing an electrode layer (40) on one side of the transport layer (32 or 33) [Fig. 2(c) and 3(d), Page 10]. Park does not teach sequentially stacking and depositing a first transport layer, a perovskite semiconductor layer (instant claim 11), and a second transport layer on at least one side of the isolation body along the preset direction. Kim teaches a preparation method for a solar cell assembly, wherein the solar cell semiconductor stack comprises a first transport layer, a perovskite semiconductor layer, and a second transport layer on at least one side of the isolation body along the preset direction [paras. 0004-0005]. The perovskite solar cell stack is disclosed to have a very special structure that exhibits insulator, semiconductor, and conductor properties, as well as superconductivity [para. 0004]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the step of sequentially stacking and depositing the semiconductor layered stack of Park to comprise sequentially stacking and depositing a first transport layer, a perovskite semiconductor layer (instant claim 11), and a second transport layer, as disclosed in Kim, for the purpose of providing a solar cell stack having a structure that exhibits insulator, semiconductor, and conductor properties, as well as superconductivity. Furthermore, such would merely involve the simple substitution of one known solar cell stack for another, and would have yielded predictable results to one of ordinary skill in the art. [MPEP 2143IB]. Regarding claim 2 Modified Park teaches the preparation method as set forth above, wherein forming the conductive layers (20) on the substrate (10) comprises: arranging a first separating member (corresponding to spacer 210 of mask M1) on the substrate (10) [Figs. 2(a) and 3(b), Pages 7 and 9], and depositing on two sides of the first separating member (210) along the preset direction to form the conductive layers (20) separated by the first trench (see patterned molybdenum layer 20) [Figs. 2(a) and 3(b), Pages 7 and 9]. Regarding claim 3 Modified Park teaches the preparation method as set forth above, wherein arranging the first separating member (210) on the substrate (10), and depositing on the two sides of the first separating member (210) along the preset direction to form the conductive layers (20) separated by the first trench (see patterned molybdenum layer 20) comprises: arranging several first separating members at intervals on the substrate along the preset direction (see Mask M1 in Fig. 3(b), wherein there are multiple separating members/spacers 210 at intervals on the substrate 10 along the preset direction); sputtering on a side surface of the substrate (10) facing the first separating members (210) in a vacuum environment (molybdenum is deposited by sputtering) [Page 9]; and removing the first separating members (210) to leave first trenches on the substrate (10), thereby forming several conductive layers (20) (after the material for forming the lower electrode layer, 20, is deposited on the substrate, the mask M1 is removed) [Page 9]. Regarding claim 4 Modified Park teaches the preparation method as set forth above, wherein arranging the isolation body (M2) on the side of the conductive layer (20) facing away from the substrate (10) comprises: simultaneously arranging the second separating member and the third separating member (spacers 310 within mask M2), which are attached to each other (via edge portion 300), on a side of each of at least part of the conductive layers (20) facing away from the substrate (10) [Fig. 2(c), Pages 7 and 10]. Regarding claim 5 Modified Park teaches the preparation method as set forth above, wherein simultaneously arranging the second separating member and the third separating member (spacers 310 within mask M2), which are attached to each other (via edge portion 300), on the side of each of at least part of the conductive layers (20) facing away from the substrate (10) comprises: simultaneously arranging the second separating member and the third separating member (both spacers 310 within mask M2 are placed simultaneously) on each conductive layer (20) along the preset direction except for conductive layers (20) located at two ends of the substrate [Figs. 2(b) and 3(b)-3(c), Page 10], and controlling (by placing on the desired position) each second separating member (see below) to be adjacent to a first side of a corresponding first trench [Figs. 2(b) and 3(b)-3(c), Pages 9-10], and the third separating member (see below) to be located on a side of the second separating member (see below) facing away from the first trench adjacent to the second separating member (patterns formed in each step of depositing a thin film must be formed at a predetermined interval offset from each other in order to manufacture a solar cell) [Pages 9-10]. PNG media_image2.png 305 535 media_image2.png Greyscale Park, Cut-out of Fig. 2(c) PNG media_image3.png 401 614 media_image3.png Greyscale Park, Cut-out of Fig. 3(c) Regarding claim 6 Modified Park teaches the preparation method as set forth above, wherein a distance D between the second separating member (310) and the adjacent first trench (having a width corresponding to that of first separating member 210) satisfies 0 μm<D≤20 μm [Park, Pages 7-8]. Regarding claim 7 Modified Park teaches the preparation method as set forth above, wherein simultaneously arranging the second separating member (310) and the third separating member (spacers 310 within mask M2), which are attached to each other (via edge portion 300), on the side of each of the at least part of the conductive layers (20) facing away from the substrate further comprises: on a conductive layer (20) located at one end of the substrate (10) and on a first side of the first trench [see Figs. 2(c) and 3(c) below, Page 10], arranging the second separating member (310) and controlling (by placing on the desired position) the second separating member (310) to be adjacent to the corresponding first trench [see Figs. 2(c) and 3(c) below, Page 10]; and on a conductive layer (20) located at another end of the substrate (10) and on a second side of the first trench [see Figs. 2(c) and 3(c) below, Page 10], arranging the third separating member (310) and controlling (by placing on the desired position) the third separating member (310) to be spaced apart from the corresponding first trench, wherein the first side and the second side face opposite directions (See opposing sides of substrate 10) [see Fig. 3(c) below, Page 10]. PNG media_image2.png 305 535 media_image2.png Greyscale Park, Cut-out of Fig. 2(c) PNG media_image3.png 401 614 media_image3.png Greyscale Park, Cut-out of Fig. 3(c) Regarding claim 9 Modified Park teaches the preparation method as set forth above, further comprising, before sequentially stacking and depositing the first transport layer, the semiconductor layer, and the second transport layer (see Kim, paras. 0004-0005; see also Park, Page 10) on the at least one side of the isolation body (M2) along the preset direction: on at least one of conductive layers (20) located at two ends of the substrate (10) along the preset direction, shielding (via first damage barrier layer 60) one side edge of the conductive layer (20) facing away from the substrate and away from the first trench (first damage barrier 60 is formed as a pair on each adjacent pair of first electrodes 20a and 20b to prevent damage to the sequential stack of the first transport layer, the semiconductor layer, and the second transport layer during the patterning process [Kim, Fig. 4 and para. 0054]. Regarding claim 10 Modified Park teaches the preparation method as set forth above, wherein thickness of the second separating member (310) and thickness of the third separating member (310) along the preset direction both range from 50 μm to 200 μm (50 to 100 μm) [Park, Page 12]. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) [MPEP 2144.05]. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kim as applied to claims 1-7 and 9-11 above, and further in view of US 2017/0194102 A1, Huang et al. Regarding claim 8 Modified Park teaches the preparation method as set forth above, wherein sequentially stacking and depositing the first transport layer, the semiconductor layer, and the second transport layer (see Kim, paras. 0004-0005; see also Park, Page 10) on the at least one side of the isolation body (M2) along the preset direction comprises: sequentially depositing the first transport layer, the semiconductor layer, and the second transport layer on the side of the conductive layer facing away from the substrate (10) [see Kim, paras. 0004-0005; see also Park, Page 10]. Modified Park does not teach the stack deposited in a in a vacuum environment. Huang teaches a preparation method for a solar cell module comprising a perovskite layer, wherein the method comprises sequentially stacking a first transport layer (122), a perovskite semiconductor layer (123), and a second transport layer (124) on a side of a conductive layer (121) facing away from a substrate (11) [Fig. 1 and para. 0031], wherein the layers are sequentially deposited in a vacuum environment (sputtering), or by spin coating, spray coating or evaporation [para. 0031]. Modified Park and Huang are analogous inventions in the field of methods for sequentially depositing perovskite solar cell stacks. Because Huang teaches choosing from a finite number of identified, predictable deposition techniques, one of ordinary skill in the art would have found obvious to pursue the known options with reasonable expectation of success [see MPEP 2143]. Since Huang teaches that sequentially depositing said stack in a vacuum environment leads to the anticipated success, said technique is not of innovation but of ordinary skill and common sense [see MPEP 2143]. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2022/0122782 A1, Jung et al. teaches a method for manufacturing a perovskite solar cell, includes disposing an electron transport layer on a transparent conductive substrate, disposing an additive-doped perovskite light absorption layer on the electron transport layer, disposing a hole transport layer on the additive-doped perovskite light absorption layer, and disposing an electrode on the hole transport layer [Abstract]. US 2021/0057169 A1, Huang et al. teaches a method for manufacturing perovskite solar cell module, comprising a first a laser scribing step for forming multi transparent conductive films (TCFs) on a transparent substrate, using a first mask to form multi HTLs, active layers, and ETLs sequentially on the TCFs, and using a second mask to form an electrical connection layer on each of the plurality of electron transport films [Abstract, Figs. 4-9 and paras. 0051-0055]. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAYLA GONZALEZ RAMOS whose telephone number is (571)272-5054. The examiner can normally be reached Monday - Thursday, 9:00-5:00 - EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allison Bourke can be reached at (303)297-4684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MAYLA GONZALEZ RAMOS/Primary Examiner, Art Unit 1721
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Prosecution Timeline

Mar 18, 2025
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
54%
Grant Probability
68%
With Interview (+13.8%)
2y 12m (~1y 8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 656 resolved cases by this examiner. Grant probability derived from career allowance rate.

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