Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the application 19/082,991 filed on 03/18/2025.
Claims 1 – 3 have been examined and are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/30/2026 and 03/18/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
Claims 1 – 3 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5 US Patent No. 10,917,641 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Current Application 19/082,991
US Patent No. 10,917,641 B2
Claim 1. An encoder comprising:
processing circuitry; and
a memory coupled to the processing circuitry,
wherein, using the memory, the processing circuitry is configured to:
change values of pixels in a first block and a second block to filter a boundary between the first block and the second block, using clipping such that change amounts of the respective values do not exceed respective thresholds, the pixels in the first block and the second block are arranged in a direction in which the first block and the second block are neighbors;
wherein the respective thresholds for the pixels in the first block and the second block are selected to be symmetrical or asymmetrical with respect to the boundary based on block sizes of the first block and the second block;
wherein the pixels in the first block include a first pixel located at a first position, and the pixels in the second block include a second pixel located at a second position corresponding to the first position with respect to the boundary;
wherein the respective thresholds include a first threshold and a second threshold corresponding to the first pixel and the second pixel, respectively;
wherein the first threshold is larger than the second threshold when the first block is larger than the second block; and
wherein a value of the first pixel is changed by using values of the pixels in the first block which are before the change of values of the pixels in the first block
1. An encoder comprising: processing circuitry; and a memory coupled to the processing circuitry, wherein, using the memory, the processing circuitry is configured to:
change values of pixels in a first block and a second block to filter a boundary between the first block and the second block, using clipping such that change amounts of the respective values do not exceed respective thresholds, the pixels in the first block and the second block are arranged in a direction in which the first block and the second block are neighbors;
wherein the respective thresholds for the pixels in the first block and the second block are selected to be symmetrical or asymmetrical with respect to the boundary based on block sizes of the first block and the second block;
wherein the pixels in the first block include a first pixel located at a first position, and the pixels in the second block include a second pixel located at a second position corresponding to the first position with respect to the boundary;
wherein the respective thresholds include a first threshold and a second threshold corresponding to the first pixel and the second pixel, respectively;
wherein the first threshold is larger than the second threshold when the first block is larger than the second block; and
pixels in the first block which are before the change of values of the pixels in the first block.
Claim 2.
Claim 5.
Claim 3.
Claim 1 but for CRM.
Nonetheless, claim 1 of the present application made the claim a broader or minimal changed with closes features version of claims 1 US Patent No. 10,917,641 B2. Therefore, since omission of an element and its function in a combination is an obvious expedient if the remaining elements perform the same functions as before (In re Karlson (CCPA) 136 USPQ 184 (1963)), claim 1 – 3 is not patentably distinct from claim claims 1 and 5 US Patent No. 10,917,641 B2.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112, second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “3. A non-transitory computer readable medium storing a bitstream, the non-transitory computer readable medium comprising::”. Claim 3 is directed to a non-transitory medium storing a bitstream clauses that appear to describe how the bitstream is generated. These elements or steps are not performed by an intended computer, and the bitstream is not a form of programming that causes functions to be performed by an intended computer. This shows that the computer-readable medium merely serves as support for storing the bitstream and provides no functional relationship between the steps/elements that describe the generation of the bitstream and intended computer system. Therefore, those claim elements are not given patentable weight. Patentable weight is given to data stored on a computer-readable medium when there exists a functional relationship between the data and its associated substrate. See MPEP 2111.05 III. For example, if a claim is drawn to a computer-readable medium containing programming, a functional relationship exists if the programming “performs some function with respect to the computer with which it is associated.”
However, if the claim recites that the computer-readable medium merely serves as a storage for information or data that is not meant for being executed, no functional relationship exists and the information or data is not given patentable weight.
The Examiner suggests that the claim be amended so that it is directed to a functional relationship. For example, in this particular case, the claim should instead be recited as “A non-transitory computer-readable media storing bitsream that when decoded by decoding device, is used by the decoding device to generate video wherein:”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 3 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pu et al. (U.S. 2015/0264363 A1).
Regarding claim 3, Pu discloses A non-transitory computer readable medium storing a bitstream (see para: 0045; This disclosure may generally refer to video encoder 20 “signaling” or “transmitting” certain information to another device, such as video decoder 30. The term “signaling” or “transmitting” may generally refer to the communication of syntax elements and/or other data used to decode the compressed video data. Such communication may occur in real- or near-real-time. Alternately, such communication may occur over a span of time, such as might occur when storing syntax elements to a computer-readable storage medium in an encoded bitstream at the time of encoding, which then may be retrieved by a decoding device at any time after being stored to this medium. Thus, while video decoder 30 may be referred to as “receiving” certain information, the receiving of information does not necessarily occur in real- or near-real-time and may be retrieved from a medium at some time after storage. [0046] Video encoder 20 and video decoder 30 each may be implemented as any of a variety of suitable circuitry, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, hardware, or any combinations thereof. If the techniques are implemented partially in software, a device may store instructions for the software in a suitable, non-transitory computer-readable storage medium and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure).
The bitstream generated by the encoder/decoder in claim 3 is merely data. Under MPEP 2111.05(III), this claim is merely machine-readable media. The Examiner finds that there is no disclosed or claimed functional relationship between the stored data and medium. Instead, the medium is merely a support or carrier for the data being stored. Therefore, the data stored and the way such data is generated should not be given patentable weight. See MPEP 2111.05 applying In re Lowry, 32 F.3d 1579, 1583-84, 32 USPQ2d 1031, 1035 (Fed. Cir. 1994) and In re Ngai, 367 F.3d 1336, 70 USPQ2d 1862 (Fed. Cir. 2004). As such, claim 3 is subject to a prior art rejection based on any non-transitory computer readable medium known before the earliest effective filing date of the present application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 – 2 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 2014/0133564 A1) in view of Yamazaki et al. (US 2014/0140416A1).
Regarding claim 1, Lim discloses: “an encoder [see para: 0006; a video encoding apparatus comprises a video encoder and a deblocking filter] comprising:
processing circuitry [see para: 0102; a processor or microprocessor to execute functions]; and a memory coupled to the processing circuitry, wherein, using the memory [Lim see para: 0019; a memory for storing various types of programs and data for encoding or decoding a video, or performing an inter or intra prediction for the encoding or decoding, and (c) a microprocessor and the like for executing the program to perform an operation and control], the processing circuitry is configured to:
change values of pixels in a first block and a second block to filter a boundary between the first block and the second block, using clipping such that change amounts of the respective values do not exceed respective thresholds, the pixels in the first block and the second block are arranged in a direction in which the first block and the second block are neighbors [see Fig. 2; para: 0046; For example, referring to FIG. 2, the deblocking filter 180 is described as performing a deblocking filtering operation of the boundary 202 located between block P and block Q. In this example, the deblocking filter operation is performed on the first row of pixels (p3,0˜q3,0). in block P and block Q. In the present disclosure, for simplicity, pixels (p3,0˜q3,0) will be referred to as (p3˜q3). The deblocking filter 180 can perform the deblocking filtering of the single row of pixels p3,0˜q3,0 by modifying the pixels in block P and block Q by the same number and/or same positions. At least one embodiment includes two pixels to modify at either side of the boundary. In at least one embodiment, the pixels included in block P are p3, p2, p1 and p0, and those included in block Q are q3, q2, q1 and q0.];
wherein the pixels in the first block include a first pixel located at a first position, and the pixels in the second block include a second pixel located at a second position corresponding to the first position with respect to the boundary [see Fig. 4; see para: 0058; According to another embodiment of the present disclosure, in performing a deblocking filtering operation for the P/Q block boundary 202 as shown in FIG. 2, the deblocking filtering operation performed by the deblocking filter 180 such that the number and/or position of pixels to be filtered in block P is different from the number and/or position of pixels to be filtered in block Q, by applying a predetermined criteria to rows of pixels included in the P and Q blocks. [0059] FIG. 4 is an exemplary diagram which illustrates a deblocking filtering operation according to at least one embodiment. [0060] As shown in FIG. 4, an example of modifying one pixel in block P and two pixels in block Q relative to the block boundary is disclosed. Besides the pixel value adjustments with the same number (e.g., 2) of pixels on both sides of the P/Q block boundary as described above, some embodiments may have pixel adjustments with a different number of pixels to be adjusted on both sides of the boundary 202];
wherein the respective thresholds include a first threshold and a second threshold corresponding to the first pixel and the second pixel, respectively [see para: 0065; In other words, with respect to the respective blocks P and Q, the pixel linearities (i.e., dp0 and dq0) are measured in the depth direction of subblocks about the block boundary 202, and the measurements are compared to a predetermined threshold (beta). For example, when condition (dp0<beta) is satisfied, filtering is carried out on p1; otherwise, no filtering is performed on the same. Likewise, when condition (dq0<beta) is satisfied, filtering is carried out on q1; otherwise, no filtering is performed on the same. In some embodiments, the threshold (beta) is set in various methods, and it may assumed to be prearranged between the video encoding apparatus 100 and video decoding apparatus 700];
wherein the first threshold is larger than the second threshold when the first block is larger than the second block [see para: 0043; In some embodiments, the predetermined criteria in the blocking filter which determines the filtering method comprises the relative sizes of blocks P, Q, or linearity as will be described later. Based on various predetermined criteria, one or more embodiments of the present disclosure can change the number and location of the pixels to be filtered by block basis or row basis]; and
wherein a value of the first pixel is changed by using values of the pixels in the first block which are before the change of values of the pixels in the first block[see para: 0043; 0047; FIG. 3 is an exemplary diagram which illustrates a deblocking filtering operation according to at least one embodiment. As shown in FIG. 3, the solid lines connect pixels before the filtering operation and the dotted lines connect the pixels after the filtering operation].
Lim does not explicitly disclose: “wherein the respective thresholds for the pixels in the first block and the second block are selected to be symmetrical or asymmetrical with respect to the boundary based on block sizes of the first block and the second block”.
However, Yamazaki, from the same or similar field of endeavor teaches: “wherein the respective thresholds for the pixels in the first block and the second block are selected to be symmetrical or asymmetrical with respect to the boundary based on block sizes of the first block and the second block [see para: 0069; FIG. 34 illustrates a case in which the EO type is restricted to the horizontal direction in the fifth embodiment of the present invention: parts (a) and (b) show cases in which reference pixels are positioned asymmetrically; and part (c) shows an overview of horizontal edges. And see para: 0072; FIG. 37 illustrates a case in which classifying is performed in accordance with the chrominance in the sixth embodiment; part (a) shows classifying performed by considering the pixel value of an achromatic color; part (b) shows classifying in which two value ranges are asymmetrically positioned with respect to the pixel values of an achromatic color. And see para: 0072; FIG. 37 illustrates a case in which classifying is performed in accordance with the chrominance in the sixth embodiment; part (a) shows classifying performed by considering the pixel value of an achromatic color; part (b) shows classifying in which two value ranges are asymmetrically positioned with respect to the pixel values of an achromatic color];
Therefore, in view of disclosures by Lim, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the de-blocking filtering process, as disclosed by Yamazaki, with the de-blocking filtering process as disclosed by Yamazaki to include the case of asymmetrical positions of pixels across block boundary, because this would amount to a simple addition of one known element by another and the result of the addition would have been predictable, namely to remove or reduce the block distortion [Yamazaki: para. 0069].
Regarding claim 2, claim 2 is rejected under the same art and evidentiary limitations as determined for the method of claim 1 but for decoder.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sato et al (US 20130028531 A1)
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/MASUM BILLAH/Primary Patent Examiner, Art Unit 2486