Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the election/restriction communication, filed 6/10/26.
Claims 2-21 were pending.
Claims 2-21 were previously restricted (Group 1: 2-5 and 12-21, Group 2: 6-11).
Applicant’s election without traverse of claims 2-5 and 12-21 in the reply filed on 6/10/26 is acknowledged.
Claims 6-11 have been canceled. Claims 2-5 and 12-21 remain pending.
The IDS, filed 5/27/25, has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-5 and 12-14, and 17-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kenan et al (US20170068451, “Kenan”).
As to claim 2:
Kenan teaches an apparatus (storage device 100; Fig. 1; 0038-0040), comprising:
a controller associated with a host system (controller of host 210; Fig. 1, 2A, 2B; 0038-0041), the controller configured to cause the apparatus to:
transmit, from the host system, a command instructing a memory system to abort one or more memory management operations associated with first data stored in the memory system (host sends command to switch from normal to burst mode; 0003-0004, 0044, 0048, 0051; this will stop current garbage collection operation to enable host write at high speed; 0003, 0076);
receive, at the host system in response to transmission of the command, an indication associated with the memory system exiting a first performance mode and entering a second performance mode (controller responds to host indication of change/switch from normal to burst mode; 0015, 0044, 0046, 0051); and
transmit, from the host system and based at least in part on receiving the indication, a write command and second data associated with the write command (host send write command and data for writing to memory in burst mode; 0002, 0044, 0050, 0062, 0063, 0066, 0073).
As to claim 3:Kenan teaches the controller is further configured to cause the apparatus to: adjust one or more parameters associated with transmitting the second data from the host system based at least in part on transmitting the command (controller controls burst write with a parameter indicative of an elapse time; 0017, 0049, 0070).
As to claim 4:
Kenan teaches the controller is further configured to cause the apparatus to: transmit third data associated with the write command after transmitting the write command and the second data associated with the write command (host transmit command and data to store in burst buffer; 0055, 0061, 0062, 0073).
As to claim 5:
Kenan teaches the write command comprises a bit indicating that the second data is associated with the second performance mode (receive indication from host for write operation in burst mode; 0004, 0044).
As to claim 12:
Kenan teaches an apparatus (storage device 100; Fig. 1; 0038-0040), comprising:
a controller associated with a memory system (controller; Fig. 1, 2A, 2B; 0038-0041) the controller configured to cause the apparatus to:
receive, at the memory system while operating in a first performance mode, a first command associated with a second performance mode (receive command to switch from normal mode to burst mode; 0004, 0044);
abort, at the memory system and based at least in part on the first command, one or more memory management operations associated with first data (host sends command to switch from normal to burst mode; 0003-0004, 0044, 0048, 0051; this will stop current garbage collection operation to enable host write at high speed; 0003, 0076);
receive, at the memory system, a second command and second data associated with the second command (host transmit command and data to store in burst buffer; 0055, 0061, 0062, 0073).; and
perform, at the memory system and based at least in part on receiving the second command and the second data, an access operation associated with the second data (perform write operation to memory in burst mode; 0002, 0044, 0050, 0062, 0063, 0066, 0073).
As to claim 13:
Kenan teaches wherein, to perform the access operation, the controller is further configured to cause the apparatus to: write the second data associated with the second command to a logical unit associated with the second performance mode (data is stored in burst buffer, which is configurable for burst mode; 0023, 0055, 0061, 0062, 0073).
As to claim 14:
Kenan teaches the controller is further configured to cause the apparatus to: receive, at the memory system, a third command to write metadata associated with the second performance mode, wherein the third command is received prior to receiving the first command (receive indication sent by host to switch to burst mode; 0004, 0044, 0060, 0062).
As to claim 17:
Kenan teaches the controller is further configured to cause the apparatus to: receive, at the memory system and prior to receiving the first command, a request for metadata associated with the memory system (host requests to write data to memory, data could be any type, such as metadata; 0024, 0050).
As to claim 18:
Kenan teaches the memory system comprises a plurality of non-volatile memory cells arranged in a plurality of logical units (data is stored to memory cells of nonvolatile memory 120; 0004, 0022, 0047, 0058; memory cells addressed with logical addresses; 0057-0059).
As to claim 19:
Kenan teaches the first data is stored in a plurality of non-volatile memory cells command (data is stored to memory cells of nonvolatile memory 120; 0004, 0022, 0047, 0058).
As to claim 20:
Kenan teaches the second command is a write command (receive write commands from host; 0002, 0044, 0062, 0063, 0066)
As to claim 21:
Kenan teaches the second performance mode is associated with a reduced write latency as compared to the first performance mode (burst mode has less latency than normal mode; 0002, 0003, 0044).
Allowable Subject Matter
Claims 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 15, the prior art does not further teach the invention of claim 14, wherein the controller is further configured to cause the apparatus to: write the metadata to a logical unit based at least in part on receiving the third command, wherein the metadata comprises a logical address range for provisioning the logical unit.
Claim 16 is allowable for incorporating the limitation of claim 15, and further limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following are some related prior arts:
US20150301763 discloses a method for adaptive burst mode in which a storage module is provided comprising a memory and a controller. The controller is configured to receive a plurality of write commands from a host controller in communication with the storage module, store the plurality of write commands in a command queue in the storage module, and choose one of a plurality of burst modes in which to operate the memory based on how many write commands are stored in the command queue.
US20150324119 discloses a method and system for improving swap performance are provided. A computing device is provided with a volatile memory and a non-volatile memory, wherein the non-volatile memory has a first swap area with multi-level cell (MLC) memory and a second swap area with single-level cell (SLC) memory. A determination is made whether the computing device is operating in normal mode or burst mode. If it is determined that the computing device is operating in normal mode, data is moved from the volatile memory to the first swap area during a swap operation. If it is determined that the computing device is operating in burst mode, data is moved from the volatile memory to the second swap area during a swap operation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAN NGUYEN whose telephone number is (571)272-4198. The examiner can normally be reached M-F 7:00am -4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached at (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THAN NGUYEN/Primary Examiner, Art Unit 2138
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