DETAILED ACTION
This action is responsive to communications filed 18 March 2025.
Claims 1-20 are subject to examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 18 March 2025 and 24 March 2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 9, 11, 14, 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sommers et al. (US-11388081-B1) hereinafter Sommers.
Regarding claim 1, Sommers discloses:
A method for impairments generation in an electronics design automation (EDA) test environment ([1:57-2:11] Methods … for impairment testing using an impairment device … for testing a system under test (SUT) and at a network test system comprising physical application-specific integrated circuit (ASIC) switching resources, see [14:35-49] test DUTs (e.g., design under testing; i.e. electronics design automation {note: specification denotes in [p. 4, l. 3-15] “EDA emulator that emulates an electronics design under test”, such that a DUT is an environment for EDA})), the method comprising:
generating, by a traffic generator in a test platform including the traffic generator ([4:46-56] traffic (e.g., packet) generator for generating test traffic, see [FIG. 7] test environment 700), an impairments module ([4:16-21] impairment testing using an impairment device), and a virtual input/output (virtIO) network driver ([7:41-56] virtual interface, see [14:10-30] ingress (Rx) virtual port resource … egress (Tx) virtual port resource), test packets and transmitting the test packets to the impairments module ([4:46-56] traffic (e.g., packet) generator for generating test traffic, see [14:35-49] test traffic is impaired using impairment device (i.e. transmitted to impairment device to be impaired));
controlling, by the impairments module ([13:36-45] impairment device), an impairment of the test packets ([13:36-45] can add or inject impairments to the link including delay, bit errors, etc., see [14:35-49] test traffic is impaired using impairment device);
transmitting, by the impairments module ([14:35-49] impairment device), to the virtIO network driver ([14:35-49] impaired traffic flow is then sent back via one or more egress lanes or portions of the associated link, see [7:41-56] virtual interface, see also [14:10-30] ingress (Rx) virtual port resource … egress (Tx) virtual port resource), and after controlling the impairment of the test packets ([13:36-45] can add or inject impairments to the link including delay, bit errors, etc., see [14:35-49] test traffic is impaired using impairment device), the test packets ([14:35-49] impaired traffic flow is then sent back via one or more egress lanes or portions of the associated link (i.e. after controlling the impairment, e.g. impaired flow is sent)); and
transmitting, by the virtIO network driver and to an EDA emulator ([7:41-56] virtual interface, see [14:10-30] ingress (Rx) virtual port resource … egress (Tx) virtual port resource, see [14:10-49] test DUTs), the test packets ([14:10-49] test environment may be configured to test DUTs (e.g., via ports ‘2’ and ‘8’ respectively) using test traffic … impaired using impairment device (i.e. impaired test packets via ports ‘2’ and ‘8’)).
Regarding claim 5, Sommers discloses:
The method of claim 1 wherein controlling the impairment of the test packets includes adding, by the impairments module, a timing impairment to the test packets ([13:36-45] inject impairments to the link including delay (i.e. timing impairment as delaying timing)).
Regarding claim 9, Sommers discloses:
The method of claim 1 comprising controlling, by the impairments module ([13:36-45] impairment device), impairment of the packets received from the EDA emulator ([19:15-20] at least some packets from SUT may be impaired by a local impairment device).
Regarding claim 20, it does not further define nor teach over the limitations of claim 1, therefore, claim 20 is rejected for at least the same reasons set forth above as in claim 1.
Regarding claim 11, Sommers discloses:
A system for impairments generation in an electronics design automation (EDA) test environment ([1:57-2:11] systems … for impairment testing using an impairment device … for testing a system under test (SUT) and at a network test system comprising physical application-specific integrated circuit (ASIC) switching resources, see [14:35-49] test DUTs (e.g., design under testing; i.e. electronics design automation {note: specification denotes in [p. 4, l. 3-15] “EDA emulator that emulates an electronics design under test”, such that a DUT is an environment for EDA})), the system comprising:
a test platform including at least one processor and a memory ([8:46-9:7] test system 102 or entities thereof (e.g., TC 104, testing applications 114, and/or RA 106) … device (e.g., a computer including at least one processor coupled to a memory) may include functionality of TC104, RA 106, and testing applications 114 [FIG. 7] test environment 700);
a traffic generator implemented by the at least one processor for generating test packets ([4:46-56] traffic (e.g., packet) generator for generating test traffic);
a virtual input/output (virtIO) network driver implemented by the at least one processor ([7:41-56] virtual interface, see [14:10-30] ingress (Rx) virtual port resource … egress (Tx) virtual port resource) for transmitting the test packets to an EDA emulator that emulates an electronics design under test ([14:10-49] test environment may be configured to test DUTs (e.g., via ports ‘2’ and ‘8’ respectively) using test traffic … impaired using impairment device (i.e. impaired test packets via ports ‘2’ and ‘8’)) and receiving packets from the electronics design under test ([19:15-20] at least some packets from SUT may be impaired by a local impairment device, see [3:46-62] test packets (e.g., to or from a SUT)); and
an impairments module implemented by the at least one processor and between the traffic generator and the virtIO network driver ([4:46-56] traffic (e.g., packet) generator for generating test traffic, see [14:35-49] test traffic is impaired using impairment device (i.e. transmitted to impairment device to be impaired) [14:10-49] test environment may be configured to test DUTs (e.g., via ports ‘2’ and ‘8’ respectively) using test traffic … impaired using impairment device (i.e. impaired test packets via ports ‘2’ and ‘8’)) for controlling impairments of the test packets transmitted to the EDA emulator and the packets received from the EDA emulator ([13:36-45] can add or inject impairments to the link including delay, bit errors, etc., see [14:35-49] test traffic is impaired using impairment device, see also [3:46-62] test packets (e.g., to or from a SUT)).
Regarding claims 14 and 18, they do not further define nor teach over the limitations of claims 5 and 9, therefore, claims 14 and 18 are rejected for at least the same reasons set forth above as in claims 5 and 9.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sommers et al. (US-11388081-B1) hereinafter Sommers in view of Sommers (US-11323354-B1) hereinafter Sommers(2).
Regarding claim 2, Sommers discloses:
The method of claim 1 set forth above,
Sommers does not explicitly disclose:
wherein generating the test packets includes generating emulated traffic of a data center processing an artificial intelligence/machine learning (AI/ML) workload.
However, Sommers(2) discloses: us11323354b1
wherein generating the test packets includes generating emulated traffic of a data center processing an artificial intelligence/machine learning (AI/ML) workload ([4:31-65] test system is adapted to include a traffic generator module for generating test traffic that is directed to flow through emulated logical switches or an emulated data center fabric … test traffic may transit the emulated data center fabric and may be received and/or processed by the DUT/SUT [6:59-7:11] generating or synthesizing test sessions, test cases, or related test packets [10:27-39] perform … machine learning (M/L)).
It would have been obvious to one of ordinary skill in the pertinent art before the effective filing date of the claimed invention to modify the invention of Sommers in view of Sommers(2) to have generated emulated traffic of a data center processing an AI/ML workload. One of ordinary skill in the art would have been motivated to do so to generate or synthesize test sessions, test cases, or related test packets to monitor the performance of the SUT/emulated switches in the emulated data center environment (Sommers(2), [6:59-7:11]).
Claim(s) 3-4, 6, 10, 12-13, 15 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sommers et al. (US-11388081-B1) hereinafter Sommers in view of Sommers (US-11765068-B2) hereinafter Sommers(3).
Regarding claim 3, Sommers discloses:
The method of claim 1 set forth above,
Sommers does not explicitly disclose:
wherein controlling the impairment of the test packets includes instructing, by the impairments module, the traffic generator to drop at least one of the test packets.
However, Sommers(3) discloses: us11765068b2
wherein controlling the impairment of the test packets includes instructing, by the impairments module, the traffic generator to drop at least one of the test packets ([8:50-61] impairment that causes one or more packets of a flow to be dropped).
It would have been obvious to one of ordinary skill in the pertinent art before the effective filing date of the claimed invention to modify the invention of Sommers in view of Sommers(3) to have dropped packets as an impairment. One of ordinary skill in the art would have been motivated to do so to emulate or approximate various traffic impairments to make sure testing mimics real world scenarios and conditions (Sommers(3), [1:42-50]).
Regarding claim 4, Sommers discloses:
The method of claim 1 set forth above,
Sommers does not explicitly disclose:
wherein controlling the impairment of the test packets includes reordering, by the impairments module, at least some of the test packets.
However, Sommers(3) discloses:
wherein controlling the impairment of the test packets includes reordering, by the impairments module, at least some of the test packets ([16:11-18] at least one impairment … may include … packet reordering).
It would have been obvious to one of ordinary skill in the pertinent art before the effective filing date of the claimed invention to modify the invention of Sommers in view of Sommers(3) to have reordered packets as an impairment. One of ordinary skill in the art would have been motivated to do so to emulate or approximate various traffic impairments to make sure testing mimics real world scenarios and conditions (Sommers(3), [1:42-50]).
Regarding claim 6, Sommers discloses:
The method of claim 5 set forth above,
Sommers does not explicitly disclose:
wherein adding the timing impairment to the test packets includes adjusting a packet inter-arrival time value carried by at least one of the test packets.
However, Sommers(3) discloses:
wherein adding the timing impairment to the test packets includes adjusting a packet inter-arrival time value carried by at least one of the test packets ([16:11-18] impairment … may include … jitter increase (i.e. adjusting inter-arrival times to increase jitter)).
It would have been obvious to one of ordinary skill in the pertinent art before the effective filing date of the claimed invention to modify the invention of Sommers in view of Sommers(3) to have adjusted a packet inter-arrival time. One of ordinary skill in the art would have been motivated to do so to emulate or approximate various traffic impairments to make sure testing mimics real world scenarios and conditions (Sommers(3), [1:42-50]).
Regarding claim 10, Sommers discloses:
The method of claim 9 wherein controlling, by the impairments module ([13:36-45] impairment device), impairment of the packets received from the EDA emulator ([19:15-20] at least some packets from SUT may be impaired by a local impairment device) includes
Sommers does not explicitly disclose:
instructing, by the impairments module, the virtIO network driver to drop at least one of the packets received from the EDA emulator and wherein the method further comprises, dropping, by the virtIO network driver, the at least one of the packets received from the EDA emulator.
However, Sommers(3) discloses:
instructing, by the impairments module ([14:10-27] impairment device(s)), the virtIO network driver to drop at least one of the packets received from the EDA emulator ([14:10-27] generate or add impairment to traffic from … DUTs, see [16:11-18] at least one impairment … may include … packet drop) and wherein the method further comprises, dropping ([8:50-61] impairment that causes one or more packets of a flow to be dropped), by the virtIO network driver, the at least one of the packets received from the EDA emulator ([14:10-34] add impairment to traffic from or to DUTs or EDCED … impaired prior to or after traversing EDCED or emulated switching fabric environment … impairments in either or both directions).
It would have been obvious to one of ordinary skill in the pertinent art before the effective filing date of the claimed invention to modify the invention of Sommers in view of Sommers(3) to have instructed the virtIO network driver to drop at least one of the packets received from the EDA emulator and performed so. One of ordinary skill in the art would have been motivated to do so to add impairments in either or both directions (Sommers(3), [14:10-34]).
Regarding claims 12-13, 15 and 19, they do not further define nor teach over the limitations of claims 3-4, 6 and 10, therefore, claims 12-13, 15 and 19 are rejected for at least the same reasons set forth above as in claims 3-4, 6 and 10.
Claim(s) 7-8 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sommers et al. (US-11388081-B1) hereinafter Sommers in view of Jackson (US-11095548-B1).
Regarding claim 7, Sommers discloses:
The method of claim 5 set forth above,
Sommers does not explicitly disclose:
wherein adding a timing impairment to the test packets includes adding a single rank timing impairment to the test packets.
However, Jackson discloses: us11095548b1
wherein adding a timing impairment to the test packets includes adding a single rank timing impairment to the test packets ([7:5-25] SDN perturbation test controller … add, e.g., fixed delay (i.e. single rank delay; e.g. a single value), see [3:54-63] impairment module).
It would have been obvious to one of ordinary skill in the pertinent art before the effective filing date of the claimed invention to modify the invention of Sommers in view of Jackson to have added a timing impairment of a single rank timing impairment. One of ordinary skill in the art would have been motivated to do so to have an impairment profile specify packet delays that are both fixed and variable (Jackson, [3:54-63]).
Regarding claim 8, Sommers discloses:
The method of claim 5 set forth above,
Sommers does not explicitly disclose:
wherein adding a timing impairment to the test packets includes adding a distributed delay timing impairment to the test packets such that different delay values are added to test packets carrying different rank IDs.
However, Jackson discloses:
wherein adding a timing impairment to the test packets includes adding a distributed delay timing impairment to the test packets such that different delay values are added to test packets carrying different rank IDs ([3:54-63] impairment module … delaying packets at a variable rate specified in an impairment profile, see [7:35-44] systematically applying the impairment profiles can include increasing a value of an impairment parameter until a threshold level of network performance degradation is reached or until a threshold rate of network performance degradation is reached … mapping … impairment profile to one or more SDN performance metric values based on monitoring the SDN test traffic (i.e. different ranks of impairments based on different rates of delays)).
It would have been obvious to one of ordinary skill in the pertinent art before the effective filing date of the claimed invention to modify the invention of Sommers in view of Jackson to have added a timing impairment that different delay values are added carrying different rank IDs. One of ordinary skill in the art would have been motivated to do so to have an impairment profile specify packet delays that are both fixed and variable (Jackson, [3:54-63]).
Regarding claims 16-17, they do not further define nor teach over the limitations of claims 7-8, therefore, claims 16-17 are rejected for at least the same reasons set forth above as in claims 7-8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Regev et al. (US-9785527-B2) Methods, Systems, And Computer Readable Media For Emulating Virtualization Resources;
Bergeron et al. (US-11729087-B2) Methods, Systems, And Computer Readable Media For Providing Adaptive Background Test Traffic In A Test Environment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Tran whose telephone number is (571)272-8173. The examiner can normally be reached Monday-Friday 10AM-6PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamal Divecha can be reached at (571)272-5863. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alex Tran/
Primary Examiner, Art Unit 2453
