Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 03/19/2025. Claims 1-14 are pending on this application.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the sum” in the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1 and 3-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. U.S. patent No. 10,970,441.
Regarding claim 1. Fig. 4C of Zhang et al. discloses a method for designing a sigma-delta converter (∑∆ ADC) comprising a step of supervised deep learning (Col. 1 lines 53-54) applied to a converter model ((∑∆ ADC), wherein: the converter model (∑∆ ADC) comprises at least one recurrent encoder (h) and at least one recurrent decoder (o); each recurrent encoder (h) is based on a generic model comprising a succession of K identical generic cells Cellk (Weight Cells in Fig. 7), with K an integer parameter greater than or equal to 1 and k an integer index ranging from 1 to K (Weight Cells in Fig. 7); the converter (∑∆ ADC) operates at an oversampling rate N (Col. 16 lines 35), with N an integer greater than or equal to 1 (oversampling output (V(t-1)….V(t+2)); each conversion by the converter (oversampling output V(t-1)….V(t+2) of ∑∆ ADC ) comprises N Cycles C[n] (t-1…t+2), where n is an integer index ranging from 1 to N (t-1….t+2); each cell Cellk (Fig. 7) of the generic model is a recurrent neural network (Col. 16 lines 30-32) which, at each cycle C[n] (t-1….t+2), calculates a product of an input vector X[n] (X(t-1)…x(t+2)) by a weight vector Wk (W; Weight program in Fig. 7) of the cell Cellk (Weight Cell in Fig. 7) ) and delivers an output vector Qk[n] (V of h(t-1)….V of h(t+2) of (∑∆ ADC)) comprising D pairs of outputs Akd[n] and Bkd[n] (V and U) for each cycle (t-1…t+2), with: D an integer greater than or equal to 1 (four of V and U pairs) and d (U of t-1…t+2) an integer index ranging from 0 to D-1 (0 to 4-1) , Akd[n] (U) the result of the product calculated (x(t-1) by the cell Cellk (Fig. 7) delayed by d cycles (t-1….t+2), Bkd[n] (V) a quantization of the result of the product calculated (h(t-1)) by the cell Cellk delayed by d cycles (t-1…t+2); and at each beginning of a cycle C[n] (t-1), vector X[n] (X) is the same for all cells Cellk (Fig. 7) and comprises, for example is equal to, the concatenation of the K vectors Qk[n] ((V of h(t-1)….V of (t+2) of (∑∆ ADC)) and of a sample x[n] (X) , for cycle C[n] (t-1…t+2), of a signal x (X) to be converted (∑∆ ADC) ,and wherein the sigma-delta converter (∑∆ ADC) is obtained by manufacturing an electronic circuit (manufacturing of Fig;. 4C) corresponding to the model obtained after the training (Col. 16 lines 26-28).
Regarding claim 3. Method according to claim 1, Fig. 4C further discloses wherein each recurrent decoder (o) is based on one or a plurality of successions of simple recurrent neural networks (Col. 16 lines 31-36).
Regarding claim 4. Method according to claim 1, Fig. 4C further discloses wherein at least one constraint determined by a material property (Col. 2 lines 64-67) or by a functional property of the converter ((∑∆ ADC) to be manufactured is applied to the converter model (manufactured of Fig. 4), preferably to each encoder (h of ∑∆ ADC).
Regarding claim 5. Method according to claim 4, Fig. 4C further discloses wherein said at least one constraint (Col. 2 lines 64-67) comprises: a constraint determined by a maximum dynamic range (range inputs X1…X7 in Fig. 7) at the output of one of the K cells Cellk (outputs of Weight Cells in Fig. 7) and corresponding to an addition of a clipping layer (Col. 29 lines 28-30) at the output of said cell Cellk (outputs of Weight Cells in Fig. 7); and/or a constraint determined by robustness to temporal non-idealities (Col. 34 lines 52-55) and corresponding to an addition on an inner node of the encoder of a data augmentation layer modeling Gaussian random noise; and/or a constraint determined by a sizing of circuits implementing weights of the encoder and corresponding to a quantization-aware training (Col. 24 lines 53-62); and/or a constraint ((Col. 2 lines 64-67) determined by a surface area of the converter to be manufactured (Fig. 4) and corresponding to a masking of encoder weights (Col. 25 lines 50-54); and/or a constraint determined by a topology of the converter to be manufactured and corresponding to a masking of encoder weights (Col. 24 lines 53-62); and/or a constraint determined by a surface area (Col. 34 line 59 to Col. 35 line 12) of the converter (Fig. 4C) and corresponding to a technique of clipping of weights of the encoder (Col. 29 lines 27-36).
Regarding claim 6. Method according to claim 1, Fig. 4C further discloses wherein at least one regularization determined by a material property ((Col. 2 lines 64-67) or by a functional property of the converter is applied to the converter model (SAR ADC) or ∑∆ ADC).
Regarding claim 7. Method according to claim 6, Fig. 4C further discloses wherein: a regularization is determined by a surface area of the converter (Col. 34 line 59 to Col. 35 line 12) be manufactured (manufactured of Fig. 4C) and corresponds to an L1 regularization applied to the encoder weights (Col. 14 lines 13-17); and/or a regularization is determined by an attenuation of inner signals (Col. 4 lines 6-8) and corresponds to a penalty (Col. 12 lines 20-30) when a weight of a loopback path (loopback path of W) of a cell Cellk (Fig. 7) is smaller than 1 (Col. 12 lines 20-30 discloses “zero weight”).
Regarding claim 8. Method according to claim 1, Fig. 4C further discloses wherein a cost function used for the training (Col. 12 lines 20-30) comprises a term determined by a regularization function (∑∆ ADC) determined by converter saturation conditions (Col. 17 lines 31-34).
Regarding claim 9. Method according to claim 7, Fig. 4C further discloses wherein the cost function (Col. 12 lines 20-30) comprises a term determined by a fidelity function (Col. 25 lines 58-67) of the type of a logarithm of the sum of the exponentials of the differences (Equation 16 on Col. 26).
Regarding claim 10. Method according to claim 1, Fig. 4C further discloses wherein the manufacturing of the converter (∑∆ ADC) comprises an implementation of each non-zero weight (Col. 12 lines 20-21) of the encoder model trained (h) by a capacitive circuit (Col. 14 lines 13-34) having a capacitance (C), a value of which is determined by said weight (Col. 14 lines 13-34).
Regarding claim 11. Method according to claim 1, Fig. 4C further discloses wherein the manufacturing of the converter ((∑∆ ADC) comprises an implementation of each non-zero weight (Col. 12 lines 20-21) of the encoder model trained (h) by a resistive circuit having a resistance (R) (Fig. 8) , a value of which is determined by said weight (Weight programing in Fig. 8).
Regarding claim 2. Method according to claim 1, Fig. 4C further discloses wherein the training is quantization-aware (Col. 17 lines 14-24).
Regarding claim 13. Method according to claim 1, Fig. 4C further discloses wherein the decoder (o) is determined by a functionality of the converter ((∑∆ ADC) to be manufactured (Col. 40 lines 1-11).
Regarding claim 14. Method according to claim 1, Fig. 4C of further disclose wherein the converter to be manufactured (∑∆ ADC) implements a cyclic (cyclic W).and alternated sampling of a plurality of input channels (X1…XN in Fig. 7) of the converter (∑∆ ADC).
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. as applied to claim 1 above, and further in view of van Veldhoven et al. Pub. No. 2025/0007532.
Fig. 4C of Zhang et al. as applied to claim 1 above further discloses wherein each recurrent encoder models a sigma-delta modulator (h) of the converter (∑∆ ADC)) and each recurrent decoder models (Digital logic “o”) to generate a digital output Y based on quantized output (V) of the converter (∑∆ ADC).
However, Zhang et al. does not disclose the recurrent decoder models (Digital logic “o”) is a digital filter.
Fig. 6 of van Veldhoven et al. discloses a method for designing a sigma-delta converter (404) comprising a digital filter (411) of the converter (404) for a recurrent neural network (468).
Zhang et al. and Veldhoven et al. are common subject matter of sigma-delta converter with recurrent neural network; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate digital filter of Veldhoven et al. into digital logic of Zhang et al. for the purpose of providing a low pass filter, a high pass or band-pass filter delay element configured to compensate for signal delays occurring within error correction system (paragraph 0048 of Veldhoven et al.) .
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
08/02/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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