DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/19/2025 and 03/05/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claims 1-11 and 19-20 are objected to because of the following informalities:
“wherein the first CXL switch and the second CXL switch which are hierarchically connected to the external host in series” in lines 12-13 of claim 1 should read as “wherein the first CXL switch and the second CXL switch
“wherein the first CXL switch and the second CXL switch which are hierarchically connected to the external host in series” in lines 15-16 of claim 19 should read as “wherein the first CXL switch and the second CXL switch
Claims 2-11 and 20 are objected to because they are dependent on the objected claims. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4 and 10-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17-20 of U.S. Patent No. 12,287,751 in view of Wang (US 2019/0235777).
Claims 5-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 6, 14, and 17 of U.S. Patent No. 12,287,751 in view of Wang (US 2019/0235777) and further in view of Bert (US 2022/0188178).
As per claims 1-20,
Instant Application
U.S. Patent No. 12,287,751 (US Application 18/131,185)
Claim 1: A computing system comprising: a first storage device; a second storage device; a memory device configured to store first map data of the first storage device and second map data of the second storage device; a first compute express link (CXL) switch connected with the first storage device and the second storage device and an external host, and configured to arbitrate communications between the first storage device and the second storage device and the external host; and a second CXL switch, connected with the first storage device and the second storage device and the memory device, configured to arbitrate communications between the first storage device and the second storage device and the memory device, wherein the first CXL switch and the second CXL switch which are hierarchically connected to the external host in series, wherein the first storage device is configured to access the first map data through the second CXL switch, and wherein the second storage device is configured to access the second map data through the second CXL switch.
Claim 17: A computing system comprising: a first storage device; a second storage device; a memory device configured to store first map data of the first storage device and second map data of the second storage device and communicate with the first storage device and the second storage device using at least two different protocols; a first compute express link (CXL) switch connected with the first storage device and the second storage device and an external host through a first interface such that the first storage device, the second storage device, and the external host communicate by a CXL.io protocol over the first interface, the first CXL switch being configured to arbitrate communications between the first storage device and the second storage device and the external host; and a second CXL switch connected with the first storage device and the second storage device and the memory device through a second interface such that the first storage device, the second storage device and the memory device communication by a CXL.mem protocol over the second interface, the second CXL switch being configured to arbitrate communications between the first storage device and the second storage device and the memory device.
Note:
Claim 17 of US Patent No. 12,287,751 teaches the italicized, bolded, and underlined limitations of instant claim 1.
Claim 17 of US Patent No. 12,287,751 does not teach the italicized limitation of instant claim 1, however the reference Wang (US 2019/0235777) teaches these limitations. See Below.
Claim 2: The computing system of claim 1, wherein the first CXL switch connected with the first storage device and the second storage device and the external host through a first interface such that the first storage device, the second storage device, and the external host communicate by a CXL.io protocol over the first interface, and wherein the second CXL switch connected with the first storage device and the second storage device and the memory device through a second interface such that the first storage device, the second storage device and the memory device communicate by a CXL.mem protocol over the second interface.
Claim 17: A computing system comprising: a first storage device; a second storage device; a memory device configured to store first map data of the first storage device and second map data of the second storage device and communicate with the first storage device and the second storage device using at least two different protocols; a first compute express link (CXL) switch connected with the first storage device and the second storage device and an external host through a first interface such that the first storage device, the second storage device, and the external host communicate by a CXL.io protocol over the first interface, the first CXL switch being configured to arbitrate communications between the first storage device and the second storage device and the external host; and a second CXL switch connected with the first storage device and the second storage device and the memory device through a second interface such that the first storage device, the second storage device and the memory device communication by a CXL.mem protocol over the second interface, the second CXL switch being configured to arbitrate communications between the first storage device and the second storage device and the memory device.
Claim 3: The computing system of claim 2, wherein the external host and the first storage device and the second storage device communicate with each other only using the CXL.io protocol.
Claim 18: The computing system of claim 17, wherein the external host and the first storage device and the second storage device communicate with each other only using the CXL.io protocol.
Claim 4: The computing system of claim 1, wherein the first storage device and the second storage device and the memory device communicate with each other only using a CXL.mem protocol.
Claim 20: The computing system of claim 19, wherein the first storage device and the second storage device and the memory device communicate with each other only using the CXL.mem protocol.
Claim 5: The computing system of claim 1, wherein the memory device comprising a first CXL memory and a second CXL memory, wherein the first CXL memory comprises a first port, wherein the second CXL memory comprises a second port, wherein the first CXL memory is connected to the second CXL switch through the first port, and wherein the second CXL memory is connected to the second CXL switch through the second port.
Claim 17 of US Patent No. 12,287,751 in view of Wang does not teach instant claim 5. However, the reference Bert (US 2022/0188178) teaches the limitations. See Below.
Claim 6: The computing system of claim 5, wherein in an initialization operation, the memory device allocates the first CXL memory as a first dedicated memory for storing the first map data of the first storage device, and wherein in the initialization operation, the memory device allocates the second CXL memory as a second dedicated memory for storing the second map data of the second storage device.
Claim 14: The operating method of claim 11, further comprising: in an initialization operation, sending, by the first storage device, a first memory allocation request for a first dedicated area of the memory device, to the memory device through the second interface, by the first storage device; in the initialization operation, sending, by the second storage device to the memory device through the third interface, a second memory allocation request for a second dedicated area of the memory device; and allocating, by the memory device, areas of the memory device as the first dedicated area and the second dedicated area, based on pre-determined priorities and based on the first memory allocation request and the second memory allocation request, wherein the first dedicated area stores first map data of the first storage device, wherein the second dedicated area stores second map data of the second storage device.
Claim 7: The computing system of claim 6, wherein the first dedicated memory is accessible only by the first storage device, and the second dedicated memory is accessible only by the second storage device.
Claim 6: The computing system of claim 1, wherein the first dedicated area is accessible only by the first storage device, and the second dedicated area is accessible only by the second storage device.
Claim 8: The computing system of claim 5, wherein in an initialization operation, the memory device allocates at least a partial area of the first CXL memory and second CXL memory as a first dedicated area for storing the first map data of the first storage device, and wherein in the initialization operation, the memory device allocates at least a partial area of the first CXL memory and second CXL memory as a second dedicated area for storing the second map data of the second storage device.
Claim 14: The operating method of claim 11, further comprising: in an initialization operation, sending, by the first storage device, a first memory allocation request for a first dedicated area of the memory device, to the memory device through the second interface, by the first storage device; in the initialization operation, sending, by the second storage device to the memory device through the third interface, a second memory allocation request for a second dedicated area of the memory device; and allocating, by the memory device, areas of the memory device as the first dedicated area and the second dedicated area, based on pre-determined priorities and based on the first memory allocation request and the second memory allocation request, wherein the first dedicated area stores first map data of the first storage device, wherein the second dedicated area stores second map data of the second storage device.
Claim 9: The computing system of claim 8, wherein the first dedicated area is accessible only by the first storage device, and the second dedicated area is accessible only by the second storage device.
Claim 6: The computing system of claim 1, wherein the first dedicated area is accessible only by the first storage device, and the second dedicated area is accessible only by the second storage device.
Claim 10: The computing system of claim 1, wherein the memory device is accessible only by the first storage device and the second storage device.
Claim 6: The computing system of claim 1, wherein the first dedicated area is accessible only by the first storage device, and the second dedicated area is accessible only by the second storage device.
Claim 11: The computing system of claim 1, wherein the first storage device is configured to send a first read request to the memory device through the second CXL switch in response to first power-off information received through the first CXL switch, wherein the second storage device is configured to send a second read request to the memory device through the second CXL switch in response to second power-off information received through the first CXL switch, and wherein the memory device configured to: schedule the first read request and the second read request based on pre-determined priorities, and process the first read request and the second read request based on a scheduling result.
Claim 5: The computing system of claim 1, wherein the first storage device is configured to send a first read request to the memory device through the second interface in response to first power-off information received through the first interface, wherein the second storage device is configured to send a second read request to the memory device through the third interface in response to second power-off information received through the first interface, and wherein the memory device configured to: schedule the first read request and the second read request based on pre-determined priorities, and process the first read request and the second read request based on a scheduling result.
Claim 12: An operating method of a computing system which includes a first storage device, a second storage device, a first compute express link (CXL) switch, a second CXL switch serially connected an external host, and a memory device, the first CXL switch connected to the first storage device and the second storage device and the external host, and the second CXL switch connected to the first storage device and the second storage device and the memory device, the operating method comprising: receiving, by the first storage device, a first read request from the external host; sending, by the first storage device, a second read request to the memory device through the second CXL switch based on the first read request; sending, by the memory device, a second read response including first partial map data to the first storage device through the second CXL switch based on the second read request; reading, by the first storage device, first user data from a nonvolatile memory of the first storage device based on the first partial map data and sending, by the first storage device, a first read response including the first user data to the external host through the first CXL switch, wherein the first CXL switch is configured to arbitrate communications between the first storage device and the second storage device and the external host, and wherein the second CXL switch is configured to arbitrate communications between the first storage device and the second storage device and the memory device.
Claim 11: An operating method of a computing system which includes a first storage device, a second storage device, a compute express link (CXL) switch, and a memory device, the first storage device and the memory device being connected through a second interface, and the second storage device and the memory device being connected through a third interface, the operating method comprising: receiving, by the first storage device, a first read request from an external host; sending, by the first storage device, a second read request to the memory device through the second interface based on the first read request; sending, by the memory device, a second read response including first partial map data to the first storage device through the second interface based on the second read request; reading, by the first storage device, first user data from a nonvolatile memory of the first storage device based on the first partial map data; sending, by the first storage device, a first read response including the first user data to the external host through a first interface; sending, by the first storage device, the first read request to the memory device through the second interface based on first power-off information received through the first interface; sending, by the second storage device, the second read request to the memory device through the third interface based on second power-off information received through the first interface; scheduling, by the memory device, the first read request and the second read request based on pre-determined priorities; and processing, by the memory device, the first read request and the second read request based on a scheduling result, by the memory device, wherein the CXL switch is connected with the first storage device and the second storage device and the external host through the first interface and arbitrates communications between the first storage device and the second storage device and the external host, and wherein the first interface, the second interface, and the third interface are based on a CXL protocol and are physically separated from each other.
Claim 17: A computing system comprising: a first storage device; a second storage device; a memory device configured to store first map data of the first storage device and second map data of the second storage device and communicate with the first storage device and the second storage device using at least two different protocols; a first compute express link (CXL) switch connected with the first storage device and the second storage device and an external host through a first interface such that the first storage device, the second storage device, and the external host communicate by a CXL.io protocol over the first interface, the first CXL switch being configured to arbitrate communications between the first storage device and the second storage device and the external host; and a second CXL switch connected with the first storage device and the second storage device and the memory device through a second interface such that the first storage device, the second storage device and the memory device communication by a CXL.mem protocol over the second interface, the second CXL switch being configured to arbitrate communications between the first storage device and the second storage device and the memory device.
Note:
Claim 11 and claim 17 of US Patent No. 12,287,751 in view of Wang teaches instant claim 11. See Below.
Claim 13: The operating method of claim 12, wherein the memory device is accessible only by the first storage device and the second storage device.
Claim 6: The computing system of claim 1, wherein the first dedicated area is accessible only by the first storage device, and the second dedicated area is accessible only by the second storage device.
Claim 14: The operating method of claim 12, further comprising: receiving, by the second storage device, a third read request from the external host; sending, by the second storage device, a fourth read request to the memory device through the second CXL switch based on the third read request sending, by the memory device, a fourth read response including second partial map data to the second storage device through the second CXL switch based on the fourth read request; reading, by the second storage device, second user data from a nonvolatile memory of the second storage device based on the second partial map data; and sending, by the second storage device, a third read response including the second user data to the external host through the first CXL switch.
Claim 12: The operating method of claim 11, further comprising: receiving, by the second storage device, a third read request from the external host; sending, by the second storage device, a fourth read request to the memory device through the third interface based on the third read request sending, by the memory device, a fourth read response including second partial map data to the second storage device through the third interface based on the fourth read request; reading, by the second storage device, second user data from a nonvolatile memory of the second storage device based on the second partial map data; and sending, by the second storage device, a third read response including the second user data to the external host through the first interface.
Claim 15: The operating method of claim 14, further comprising: after receiving the second read request and the fourth read request, scheduling, by the memory device, the fourth read request based on pre-determined priorities so that the fourth read request is processed prior to the second read request.
Claim 13: The operating method of claim 12, further comprising: after receiving the second read request and the fourth read request, scheduling, by the memory device, the fourth read request based on pre-determined priorities so that the fourth read request is processed prior to the second read request.
Claim 16: The operating method of claim 12, further comprising: in an initialization operation, sending, by the first storage device, a first memory allocation request for a first dedicated area of the memory device, to the memory device through the second CXL switch, by the first storage device; in the initialization operation, sending, by the second storage device to the memory device through the second CXL switch, a second memory allocation request for a second dedicated area of the memory device; and allocating, by the memory device, areas of the memory device as the first dedicated area and the second dedicated area, based on pre-determined priorities and based on the first memory allocation request and the second memory allocation request, wherein the first dedicated area stores first map data of the first storage device, wherein the second dedicated area stores second map data of the second storage device.
Claim 14: The operating method of claim 11, further comprising: in an initialization operation, sending, by the first storage device, a first memory allocation request for a first dedicated area of the memory device, to the memory device through the second interface, by the first storage device; in the initialization operation, sending, by the second storage device to the memory device through the third interface, a second memory allocation request for a second dedicated area of the memory device; and allocating, by the memory device, areas of the memory device as the first dedicated area and the second dedicated area, based on pre-determined priorities and based on the first memory allocation request and the second memory allocation request, wherein the first dedicated area stores first map data of the first storage device, wherein the second dedicated area stores second map data of the second storage device.
Claim 17: The operating method of claim 16, wherein the allocating includes: allocating at least a partial area of the memory device as the first dedicated area based on the first memory allocation request; and after allocating the first dedicated area, allocating at least a partial area of the memory device as the second dedicated area based on the second memory allocation request, wherein the first storage device has a high priority, and the second storage device has a medium priority.
Claim 15: The operating method of claim 14, wherein the allocating includes: allocating at least a partial area of the memory device as the first dedicated area based on the first memory allocation request; and after allocating the first dedicated area, allocating at least a partial area of the memory device as the second dedicated area based on the second memory allocation request, wherein the first storage device has a high priority, and the second storage device has a medium priority.
Claim 18: The operating method of claim 12, further comprising: in an initialization operation, sending, by the first storage device to the memory device, a first memory allocation request including first characteristic information indicating a type or importance of data stored in the first storage device; in the initialization operation, sending, by the second storage device to the memory device, a second memory allocation request including second characteristic information indicating a type or importance of data stored in the second storage device; and determining, by the memory device, priorities of the first storage device and the second storage device based on the first characteristic information and the second characteristic information.
Claim 16: The operating method of claim 11, further comprising: in an initialization operation, sending, by the first storage device to the memory device, a first memory allocation request including first characteristic information indicating a type or importance of data stored in the first storage device; in the initialization operation, sending, by the second storage device to the memory device, a second memory allocation request including second characteristic information indicating a type or importance of data stored in the second storage device; and determining, by the memory device, priorities of the first storage device and the second storage device based on the first characteristic information and the second characteristic information.
Claim 19: A computing system comprising: a first storage device comprising first nonvolatile memory; a second storage device comprising second nonvolatile memory; a memory device comprising a processor, a buffer memory interface circuit and a buffer memory, configured to store first map data of the first storage device and second map data of the second storage device; a first compute express link (CXL)switch connected with the first storage device and the second storage device and an external host through a first interface, and configured to arbitrate communications between the first storage device and the second storage device and the external host; and a second CXL switch connected with the first storage device and the second storage device and the memory device through a second interface, configured to arbitrate communications between the first storage device and the second storage device and the memory device, wherein the first CXL switch and the second CXL switch which are hierarchically connected to the external host in series, and wherein the first interface and the second interface are based on a CXL protocol.
Claim 17: A computing system comprising: a first storage device; a second storage device; a memory device configured to store first map data of the first storage device and second map data of the second storage device and communicate with the first storage device and the second storage device using at least two different protocols; a first compute express link (CXL) switch connected with the first storage device and the second storage device and an external host through a first interface such that the first storage device, the second storage device, and the external host communicate by a CXL.io protocol over the first interface, the first CXL switch being configured to arbitrate communications between the first storage device and the second storage device and the external host; and a second CXL switch connected with the first storage device and the second storage device and the memory device through a second interface such that the first storage device, the second storage device and the memory device communication by a CXL.mem protocol over the second interface, the second CXL switch being configured to arbitrate communications between the first storage device and the second storage device and the memory device.
Claim 20: The computing system of claim 19, wherein the first interface is a CXL.io protocol, and the second interface is a CXL.mem protocol.
Claim 17: A computing system comprising: a first storage device; a second storage device; a memory device configured to store first map data of the first storage device and second map data of the second storage device and communicate with the first storage device and the second storage device using at least two different protocols; a first compute express link (CXL) switch connected with the first storage device and the second storage device and an external host through a first interface such that the first storage device, the second storage device, and the external host communicate by a CXL.io protocol over the first interface, the first CXL switch being configured to arbitrate communications between the first storage device and the second storage device and the external host; and a second CXL switch connected with the first storage device and the second storage device and the memory device through a second interface such that the first storage device, the second storage device and the memory device communication by a CXL.mem protocol over the second interface, the second CXL switch being configured to arbitrate communications between the first storage device and the second storage device and the memory device.
Claim 17 of US Patent 12,287,751 discloses a computing system comprising first and second storage devices and a memory device coupled to first and second CXL switches further coupled to an external host, which instant claim 1 also discloses.
Claim 17 of US Patent 12,287,751 does not teach the computing system comprising wherein the first CXL switch and the second CXL switch which are hierarchically connected to the external host in series.
These limitations are however known in the art as shown in Wang (US 2019/0235777). Wang teaches the computing system comprising wherein the first CXL switch and the second CXL switch which are hierarchically connected to the external host in series (Fig. 3, Two non-ethernet switches shown coupled in a hierarchical series connection; Paragraph 0067, FIG. 3… includes at least two Non-Ethernet switches… Paragraph 0057, Non-Ethernet network may use the native protocol of the physical storage medium as networking protocol. In this case, the native protocol of the physical storage medium includes… CXL(Compute Express Link)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified US Patent 12,287,751’s computing system of claim 17 to incorporate the teachings of Wang and include multiple CXL switches coupled hierarchically and redundantly to the storage devices in order to yield the obvious result of utilizing the well-known and commonly used CXL protocol to provide high-speed and high-capacity data transfer, thus creating a flexible high-capacity data storage system (See Wang: Paragraphs 0012 and 0013).
Instant claims 11 and 19 are similar to instant claim 1 and thus instant claim 11 is rejected over claims 11 and 17 of US Patent 12,287,751 in view of Wang and instant claim 19 is rejected over claim 17 of US Patent 12,287,751 in view of Wang under similar rationale, respectively. It would have been obvious to incorporate the operating method of claim 11 of US Patent 12,287,751 with the computing system of claim 17 of US Patent 12,287,751 because they are the same embodiment and a computing system is well-known to run operating methods to achieve their functions.
Dependent claims 2-4, 10, 12-18, and 20 of Instant Application are rejected over claims 5-6, 11-18, and 20 of US Patent 12,287,751 in view of Wang. See Table Above.
Claims 5-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 6, 14, and 17 of U.S. Patent No. 12,287,751 in view of Wang (US 2019/0235777) and further in view of Bert (US 2022/0188178).
Regarding instant claim 5, claim 17 of US Patent 12,287,751 in view of Wang teaches the computing system of instant claim 1. Claim 17 of US Patent 12,287,751 in view of Wang does not teach the computing system comprising wherein the memory device comprising a first CXL memory and a second CXL memory, wherein the first CXL memory comprises a first port, wherein the second CXL memory comprises a second port, wherein the first CXL memory is connected to the second CXL switch through the first port, and wherein the second CXL memory is connected to the second CXL switch through the second port.
Bert teaches the computing system comprising wherein the memory device (Fig. 1, Memory sub-system 110 comprising first and second CXL memory devices 130 and 140) comprising a first CXL memory and a second CXL memory (Fig. 1, First and second CXL memory devices 130/140 and Fig. 4, first and second CXL memory devices 420-1/420-2 are the same embodiment; Paragraph 0056, FIG. 4 is a block diagram of a visibility configuration of a system 400 that can implement node coherency for storage related data, in accordance with some embodiments of the present disclosure… Paragraph 0060, Each of the memory devices includes a number of volumes, with each of the volumes including a port… each port can correspond to the interface standard (e.g., PCIe or CXL)), wherein the first CXL memory comprises a first port (Fig. 4, First port 421-1 of device 420-1), wherein the second CXL memory comprises a second port (Fig. 4, Second port 421-2 of device 420-2), wherein the first CXL memory is connected to the second CXL switch through the first port (Fig. 4, Device 420-1 (i.e. first CXL memory) connected to switch domain 430-2 (i.e. second CXL switch) via port 421-1 (i.e. first port)), and wherein the second CXL memory is connected to the second CXL switch through the second port (Fig. 4, Device 420-2 (i.e. second CXL memory) connected to switch domain 430-2 (i.e. second CXL switch) via port 421-2 (i.e. second port)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified US Patent 12,287,751’s computing system of claim 17 in view of Wang to incorporate the teachings of Bert and include multiple CXL memory devices coupled to the second switch in order to provide redundancy during system failure using fast storage memory types while reducing costs (See Bert: Paragraphs 0015-0017 and 0019-0020).
Dependent claims 6-9 of the instant application are rejected in view of claims 6, 14, and 17 of U.S. Patent No. 12,287,751 in view of Wang (US 2019/0235777) and further in view of Bert (US 2022/0188178). See Table Above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, 12-14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hahn (US 2023/0176744) in view of Wang (US 2019/0235777).
Regarding claim 1, Hahn teaches a computing system (Figs. 2 and 3, Computing system 300, i.e. computing system 300 is equivalent to Fig. 2, computing system 200; Paragraph 0034, Aspects of the storage system 300 may be similar to the storage system 200 of FIG. 2) comprising: a first storage device (Fig. 3, First data storage device 306a); a second storage device (Fig. 3, Second data storage device 306b, i.e. first/second data storage devices 306a/b are equivalent to Fig. 2, data storage device 212); a memory device (Fig. 3, DRAM pool 324, i.e. DRAM pool 324 is equivalent to Fig. 2, DRAM pool 210) configured to store first map data of the first storage device (Fig. 2, DRAM pool 210 (i.e. Fig. 3, DRAM pool 324) stores the corresponding L2P mapping tables (i.e. first and second map data) of Fig. 2, data storage device 212 (i.e. Fig. 3, data storage devices 306a/b); Paragraph 0033, L2P table of the data storage device 212 may be stored in a DRAM device of the DRAM pool 210) and second map data of the second storage device (Fig. 3, DRAM pool 324 contains DRAM storage devices that store corresponding L2P mapping tables (i.e. first and second map data) of the data storage devices 306a/b (i.e. first and second storage devices); Paragraph 0038, read access to L2P entries stored in the DRAM pool 324… Paragraph 0039, allocating… DRAM devices from the DRAM pool 324 to the first data storage device 306a and the second data storage device 306b); and a first switch (Fig. 3, PCIe switch 304) connected with the first storage device, the second storage device, and an external host (Fig. 3, Host device 302 (i.e. an external host) communicates to data storage devices 306a/b (i.e. first storage device and second storage device) via the PCIe switch 304), and configured to arbitrate communications between the first storage device, the second storage device, and the external host (Fig. 3, PCIe switch 304 decides where to route requests between data storage devices 306a/b (i.e. arbitrates request/response transmission) and performs prioritization; See Paragraph 0038), a second switch (Figs. 2 and 3, DRAM HMB controller 208 in Figure 2 and 326 in Figure 3, respectively), connected with the first storage device and the second storage device and the memory device (Figs. 2 and 3, DRAM HMB controller 326 switches between data storage device 306a and data storage device 306b and the DRAM pool 324), configured to arbitrate communications between the first storage device and the second storage device and the memory device (Fig. 3, DRAM HMB controller 326 acts as a root complex thus arbitrating access to DRAM pool 324; Paragraph 0037, DRAM HMB controller 326 may act as a root complex for one or more data storage devices), wherein the first switch and the second switch are hierarchically connected to the external host in series (Fig. 2, DRAM HMB controller 208 (i.e. second switch) couples hierarchically to PCIe switch 204 (i.e. first switch) in series to host device 202 (i.e. external host)), wherein the first storage device is configured to access the first map data through the second switch (Figs. 2 and 3, HMB controller 214 and 312 (i.e. first storage device 306a of Fig. 3), respectively, accesses L2P table (i.e. first map data) through DRAM HMB controller 208 and 326 (i.e. second switch), respectively; Paragraph 0033, LBA to PBA mapping of the data may be stored in a L2P table… HMB controller 214 may access the controller unit 206 as an external storage device in order to store and retrieve L2P descriptors), and wherein the second storage device is configured to access the second map data through the second switch (Figs. 2 and 3, HMB controller 214 and 312 of data storage device 306b (i.e. second storage device), respectively, also accesses L2P table; Paragraph 0039, DRAM HMB controller 326 may be responsible for allocating one or more DRAM devices from the DRAM pool 324 to the first data storage device 306a and the second data storage device 306b… Paragraph 0045, HMB controller 214 sends a read command to the DRAM HMB controller 208 to retrieve data from the L2P table corresponding to the read command).
Hahn does not teach the computing system comprising a first CXL switch and a second CXL switch.
Wang teaches the computing system comprising a first CXL switch and a second CXL switch (Fig. 3, Two non-ethernet switches shown coupled in a hierarchical series connection; Paragraph 0067, FIG. 3… includes at least two Non-Ethernet switches… Paragraph 0057, Non-Ethernet network may use the native protocol of the physical storage medium as networking protocol. In this case, the native protocol of the physical storage medium includes… CXL(Compute Express Link)).
Hahn and Wang are analogous arts because they are in the same field of endeavor of switching between external host/servers and storage devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hahn’s computing system to incorporate the teachings of Wang and include multiple CXL switches coupled redundantly to the storage devices of Hahn.
One of ordinary skill in the art would be motivated to make the modifications in order to yield the obvious result of utilizing the well-known and commonly used CXL protocol to provide high-speed and high-capacity data transfer, thus creating a flexible high-capacity data storage system (See Wang: Paragraphs 0012 and 0013).
Regarding claim 10, Hahn in view of Wang teaches the computing system of claim 1. Hahn teaches the computing system comprising wherein the memory device is accessible only by the first storage device and the second storage device (Fig. 3, Only HMB controllers 312 of each data storage device 306a/b (i.e. first storage device and second storage device) have direct access to the DRAM pool 324; Paragraph 0048, DRAM pool is shared by the one or more data storage devices).
Regarding claim 12, Hahn teaches an operating method of a computing system (Fig. 3, Computing system 300) which includes a first storage device (Fig. 3, First data storage device 306a), a second storage device (Fig. 3, Second data storage device 306b), a first switch (Fig. 3, PCIe switch 304), a second switch serially connected to an external host (Figs. 2 and 3, DRAM HMB controller 326 switches between data storage device 306a and data storage device 306b and the DRAM pool 324 and is serially connected to host device 302 (i.e. an external host) from PCIe switch 304 (i.e. PCIe is a serial protocol)), and a memory device (Fig. 3, DRAM pool 324), the first switch connected to the first storage device and the second storage device and the external host (Fig. 3, Host device 302 (i.e. an external host) communications via a single interface (i.e. a first interface) to data storage devices 306a/b (i.e. first storage device and second storage device) via the PCIe switch 304), and the second switch connected to the first storage device and the second storage device and the memory device (Figs. 2 and 3, DRAM HMB controller 326 switches between data storage device 306a and data storage device 306b and the DRAM pool 324), the operating method comprising: receiving, by the first storage device, a first read request from an external host (Fig. 6, Data storage device controller receives read command from host in step 602; Paragraph 0044, block 602, a controller of the data storage device 212, such as the HMB controller 214, receives a read command from the host device 202); sending, by the first storage device, a second read request to the memory device through the second switch based on the first read request (Fig. 6, L2P table read request is sent to the memory device (i.e. Fig. 3, DRAM pool 324) by the data storage device in step 604 via port 310 in Figure 3 to DRAM HMB controller 326 (i.e. second switch)); sending, by the memory device, a second read response including first partial map data to the first storage device through the second switch based on the second read request (Fig. 6, Retrieve L2P table (i.e. a second read response) from the memory device via DRAM HMB controller 326 (i.e. second switch)); reading, by the first storage device, first user data from a nonvolatile memory of the first storage device based on the first partial map data (Fig. 6, Data storage device reads data from the nonvolatile memory (Fig. 2, Nonvolatile memory 222 within the data storage device 212) of the data storage device using the L2P table information in step 608; See Paragraph 0045); and sending, by the first storage device, a first read response including the first user data to the external host through a first interface (Fig. 6, Data storage device delivers data to the host device in step 608; Paragraph 0045, block 608, the data is read from the memory device 222 using the retrieved L2P table information and the data is delivered to the host device 202); wherein the first switch (Fig. 3, PCIe switch 304) is configured to arbitrate communications between the first storage device and the second storage device and the external host (Fig. 3, PCIe switch 304 decides where to route requests between data storage devices 306a/b (i.e. arbitrates request/response transmission) and performs prioritization; See Paragraph 0038), and wherein the second switch is configured to arbitrate communications between the first storage device and the second storage device and the memory device (Fig. 3, DRAM HMB controller 326 (i.e. second switch) acts as a root complex and thus arbitrates between data storage device 306a and data storage device 306b to determine which has access; Paragraph 0037, DRAM HMB controller 326 may act as a root complex for one or more data storage devices).
Hahn does not teach the operating method comprising a first CXL switch and a second CXL switch.
Wang teaches the operating method comprising a first CXL switch and a second CXL switch (Fig. 3, Two non-ethernet switches shown coupled in a hierarchical series connection; Paragraph 0067, FIG. 3… includes at least two Non-Ethernet switches… Paragraph 0057, Non-Ethernet network may use the native protocol of the physical storage medium as networking protocol. In this case, the native protocol of the physical storage medium includes… CXL(Compute Express Link)).
Hahn and Wang are analogous arts because they are in the same field of endeavor of switching between external host/servers and storage devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hahn’s operating method to incorporate the teachings of Wang and include multiple CXL switches coupled redundantly to the storage devices of Hahn.
One of ordinary skill in the art would be motivated to make the modifications in order to yield the obvious result of utilizing the well-known and commonly used CXL protocol to provide high-speed and high-capacity data transfer, thus creating a flexible high-capacity data storage system (See Wang: Paragraphs 0012 and 0013).
Regarding claim 13, Hahn in view of Wang teaches the operating method of claim 12. Hahn teaches the operating method comprising wherein the memory device is accessible only by the first storage device and the second storage device (Fig. 3, Only HMB controllers 312 of each data storage device 306a/b (i.e. first storage device and second storage device) have direct access to the DRAM pool 324; Paragraph 0048, DRAM pool is shared by the one or more data storage devices).
Regarding claim 14, Hahn in view of Wang teaches the operating method of claim 13. Hahn teaches the operating method further comprising: receiving, by the second storage device, a third read request from the external host (Fig. 6, Second data storage device controller (i.e. Fig. 3, second data controller 306b) receives second read command from host in step 602; Paragraph 0044, block 602, a controller of the data storage device 212, such as the HMB controller 214, receives a read command from the host device 202); sending, by the second storage device, a fourth read request to the memory device through the second switch based on the third read request (Fig. 6, L2P table read request is sent to the memory device (Fig. 3, DRAM pool 324) by the data storage device in step 604 via port 310 and DRAM HMB controller 326 (i.e. second switch) in Figure 3); sending, by the memory device, a fourth read response including second partial map data to the second storage device through the second switch based on the fourth read request (Fig. 6, Retrieve L2P table (i.e. a second read response) from the memory device by the data storage device in step 604 via port 310 and DRAM HMB controller 326 (i.e. second switch) in Figure 3); reading, by the second storage device, second user data from a nonvolatile memory of the second storage device based on the second partial map data (Fig. 6, Second data storage device reads data from the nonvolatile memory (i.e. Fig. 2, nonvolatile memory 222 within the data storage device 212) of the data storage device using the L2P table information in step 608; See Paragraph 0045); and sending, by the second storage device, a third read response including the second user data to the external host through the first switch (Fig. 6, Data storage device delivers data to the host device in step 608 via PCIe switch 304 in Figure 3; Paragraph 0045, block 608, the data is read from the memory device 222 using the retrieved L2P table information and the data is delivered to the host device 202).
Wang teaches the operating method comprising a first CXL switch and a second CXL switch (Fig. 3, Two non-ethernet switches shown coupled in a hierarchical series connection; Paragraph 0067, FIG. 3… includes at least two Non-Ethernet switches… Paragraph 0057, Non-Ethernet network may use the native protocol of the physical storage medium as networking protocol. In this case, the native protocol of the physical storage medium includes… CXL(Compute Express Link)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hahn’s operating method to incorporate the teachings of Wang and include multiple CXL switches coupled redundantly to the storage devices of Hahn.
One of ordinary skill in the art would be motivated to make the modifications in order to yield the obvious result of utilizing the well-known and commonly used CXL protocol to provide high-speed and high-capacity data transfer, thus creating a flexible high-capacity data storage system (See Wang: Paragraphs 0012 and 0013).
Regarding claim 19, Hahn teaches a computing system (Figs. 2 and 3, Computing system 300, i.e. computing system 300 is equivalent to Fig. 2, computing system 200; Paragraph 0034, Aspects of the storage system 300 may be similar to the storage system 200 of FIG. 2) comprising: a first storage device comprising first nonvolatile memory (Fig. 3, First data storage device 306a with first nonvolatile memory 320); a second storage device comprising second nonvolatile memory (Fig. 3, Second data storage device 306b with second nonvolatile memory 320); a memory device (Fig. 4, Controller unit 402) comprising a processor (Fig. 4, Root complex/port 404), a buffer memory interface circuit (Fig. 4, CMB controller 406) and a buffer memory (Fig. 4, DRAM pool 408 which is the same as DRAM pool 324 in Figure 3), configured to store first map data of the first storage device (Fig. 2, DRAM pool 210 (i.e. Fig. 3, DRAM pool 324) stores the corresponding L2P mapping tables (i.e. first and second map data) of Fig. 2, data storage device 212 (i.e. Fig. 3, data storage devices 306a/b); Paragraph 0033, L2P table of the data storage device 212 may be stored in a DRAM device of the DRAM pool 210) and second map data of the second storage device (Fig. 3, DRAM pool 324 contains DRAM storage devices that store corresponding L2P mapping tables (i.e. first and second map data) of the data storage devices 306a/b (i.e. first and second storage devices); Paragraph 0038, read access to L2P entries stored in the DRAM pool 324… Paragraph 0039, allocating… DRAM devices from the DRAM pool 324 to the first data storage device 306a and the second data storage device 306b); and a first switch (Fig. 3, PCIe switch 304) connected with the first storage device, the second storage device, and an external host through a first interface (Fig. 3, Host device 302 (i.e. an external host) communicates to data storage devices 306a/b (i.e. first storage device and second storage device) via the PCIe switch 304 via first interface between 302 and 304), and configured to arbitrate communications between the first storage device, the second storage device, and the external host (Fig. 3, PCIe switch 304 decides where to route requests between data storage devices 306a/b (i.e. arbitrates request/response transmission) and performs prioritization; See Paragraph 0038); and a second switch (Fig. 4, Root complex 404 acts as a switch between data storage devices 306 a/b), connected with the first storage device and the second storage device and the memory device through a second interface (Fig. 4, Root complex 404 arbitrates between data storage devices 306a/b and DRAM pool 408 via the second interface between 404 and 406), configured to arbitrate communications between the first storage device and the second storage device and the memory device (Fig. 3, Root complex 404 arbitrates access to DRAM pool 324; Paragraph 0041, root complex/port 1 404, which may be able to connect to multiple data storage devices), wherein the first switch and the second switch are hierarchically connected to the external host in series (Fig. 4, Root complex 404 (i.e. second switch) couples hierarchically to PCIe switch 304 (i.e. first switch) in series to host device 302 (i.e. external host)).
Hahn does not teach the computing system comprising a first CXL switch and a second CXL switch, and wherein the first interface and the second interface are based on a CXL protocol.
Wang teaches the computing system comprising a first CXL switch and a second CXL switch (Fig. 3, Two non-ethernet switches shown coupled in a hierarchical series connection; Paragraph 0067, FIG. 3… includes at least two Non-Ethernet switches… Paragraph 0057, Non-Ethernet network may use the native protocol of the physical storage medium as networking protocol. In this case, the native protocol of the physical storage medium includes… CXL(Compute Express Link)).
Hahn and Wang are analogous arts because they are in the same field of endeavor of switching between external host/servers and storage devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hahn’s computing system to incorporate the teachings of Wang and include multiple CXL switches coupled redundantly to the storage devices of Hahn.
One of ordinary skill in the art would be motivated to make the modifications in order to yield the obvious result of utilizing the well-known and commonly used CXL protocol to provide high-speed and high-capacity data transfer, thus creating a flexible high-capacity data storage system (See Wang: Paragraphs 0012 and 0013).
Claims 2-4 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hahn (US 2023/0176744) in view of Wang (US 2019/0235777) and further in view of Lanka (US 2020/0394150).
Regarding claim 2, Hahn in view of Wang teaches the computing system of claim 1. Hahn teaches the computing system comprising wherein the first switch connected with the first storage device and the second storage device and the external host through a first interface such that the first storage device, the second storage device, and the external host communicate by a protocol over the first interface (Fig. 3, PCIe switch 304 (i.e. first switch) is coupled to host device 302 (i.e. external device), data storage device 306a (i.e. first storage device), and data storage device 306b (i.e. second storage device) via an interface between 302 and 304 (i.e. first interface) and uses PCIe protocol), and wherein the second switch connected with the first storage device and the second storage device and the memory device through a second interface such that the first storage device, the second storage device, and the memory device communicate by a protocol over the second interface (Fig. 3, DRAM HMB controller 326 (i.e. second switch) is coupled to DRAM pool 324 (i.e. memory device), data storage device 306a (i.e. first storage device), and data storage device 306b (i.e. second storage device) via an interface between 326 and 324 (i.e. second interface) and uses PCIe protocol; Paragraph 0033, controller unit 206 may appear to the data storage device 212 as a peer PCIe device and may be addressed using standard PCIe methods).
Neither Hahn nor Wang teaches the computing system comprising wherein the first CXL switch communicate by a CXL.io protocol over the first interface, and wherein the second CXL switch communicate by a CXL.mem protocol over the second interface.
Lanka teaches the computing system comprising wherein the first CXL switch communicate by a CXL.io protocol over the first interface (Fig. 5, First switch 555b communicates using CXL.io protocol 535b via a first interface; Paragraph 0055, CXL multiplexing logic (e.g., 555a-b) may also be provided to enable multiplexing of CXL protocols (e.g., I/O protocol 535a-b (e.g., CXL.io), caching protocol 540a-b (e.g., CXL.cache), and memory access protocol 545a-b (CXL.mem))), and wherein the second CXL switch communicate by a CXL.mem protocol over the second interface (Fig. 5, Second switch 555a communicates using CXL.mem protocol 545a via a second interface; See Paragraph 0055).
Hahn, Wang, and Lanka are analogous arts because they are in the same field of endeavor of switching between external host/servers and storage devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hahn/Wang’s computing system to incorporate the teachings of Lanka and include CXL.IO protocol on the first switch and CXL.MEM protocol on the second switch of Hahn/Wang.
One of ordinary skill in the art would be motivated to make the modifications in order to provide CXL protocols that enable support for multiple heterogeneous memory types while providing data coherency between different devices in a low-latency and high-bandwidth communication link over the well-established and widely adopted PCIe infrastructure (See Lanka: Paragraphs 0054 and 0062).
Regarding claim 3, the combination of Hahn/Wang/Lanka teaches the computing system of claim 2. Hahn teaches the computing system comprising wherein the external host and the first storage device and the second storage device communicate with each other only using the protocol (Fig. 3, PCIe switch 304 uses only the PCIe protocol between host 302 and devices 306a/b).
Lanka teaches the computing system comprising communicate with each other only using the CXL.io protocol (Fig. 5, First switch 555b can be implemented with only the CXL.io protocol; Paragraph 0054, Based on the particular accelerator usage model, all of the CXL protocols or only a subset of the protocols may be enabled).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hahn/Wang’s computing system to incorporate the teachings of Lanka and include CXL.IO protocol on the first switch and CXL.MEM protocol on the second switch of Hahn/Wang.
One of ordinary skill in the art would be motivated to make the modifications in order to provide CXL protocols that enable support for multiple heterogeneous memory types while providing data coherency between different devices in a low-latency and high-bandwidth communication link over the well-established and widely adopted PCIe infrastructure (See Lanka: Paragraphs 0054 and 0062).
Regarding claim 4, Hahn in view of Wang teaches the computing system of claim 1. Hahn teaches the computing system comprising wherein the first storage device and the second storage device and the memory device communicate with each other only using a protocol (Fig. 3, DRAM pool 324 and data storage devices 306a/b use PCIe standard; Paragraph 0033, controller unit 206 may appear to the data storage device 212 as a peer PCIe device and may be addressed using standard PCIe methods).
Neither Hahn nor Wang teaches the computing system comprising communicate with each other only using the CXL.mem protocol.
Lanka teaches the computing system comprising communicate with each other only using the CXL.mem protocol (Fig. 5, Second switch 555a can be implemented with only the CXL.mem protocol; Paragraph 0054, Based on the particular accelerator usage model, all of the CXL protocols or only a subset of the protocols may be enabled).
Hahn, Wang, and Lanka are analogous arts because they are in the same field of endeavor of switching between external host/servers and storage devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hahn/Wang’s computing system to incorporate the teachings of Lanka and include CXL.IO protocol on the first switch and CXL.MEM protocol on the second switch of Hahn/Wang.
One of ordinary skill in the art would be motivated to make the modifications in order to provide CXL protocols that enable support for multiple heterogeneous memory types while providing data coherency between different devices in a low-latency and high-bandwidth communication link over the well-established and widely adopted PCIe infrastructure (See Lanka: Paragraphs 0054 and 0062).
Regarding claim 20, Hahn in view of Wang teaches the computing system of claim 19.
Neither Hahn nor Wang teaches the computing system comprising wherein the first interface is a CXL.io protocol, and wherein the second interface communicate is a CXL.mem protocol.
Lanka teaches the computing system comprising wherein the first interface is a CXL.io protocol (Fig. 5, First switch 555b communicates using CXL.io protocol 535b via a first interface; Paragraph 0055, CXL multiplexing logic (e.g., 555a-b) may also be provided to enable multiplexing of CXL protocols (e.g., I/O protocol 535a-b (e.g., CXL.io), caching protocol 540a-b (e.g., CXL.cache), and memory access protocol 545a-b (CXL.mem))), and wherein the second interface communicate is a CXL.mem protocol (Fig. 5, Second switch 555a communicates using CXL.mem protocol 545a via a second interface; See Paragraph 0055).
Hahn, Wang, and Lanka are analogous arts because they are in the same field of endeavor of switching between external host/servers and storage devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hahn/Wang’s computing system to incorporate the teachings of Lanka and include CXL.IO protocol on the first switch and CXL.MEM protocol on the second switch of Hahn/Wang.
One of ordinary skill in the art would be motivated to make the modifications in order to provide CXL protocols that enable support for multiple heterogeneous memory types while providing data coherency between different devices in a low-latency and high-bandwidth communication link over the well-established and widely adopted PCIe infrastructure (See Lanka: Paragraphs 0054 and 0062).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hahn (US 2023/0176744) in view of Wang (US 2019/0235777) and further in view of Bert (US 2022/0188178).
Regarding claim 5, Hahn in view of Wang teaches the computing system of claim 1.
Neither Hahn nor Wang teaches the computing system comprising wherein the memory device comprising a first CXL memory and a second CXL memory, wherein the first CXL memory comprises a first port, wherein the second CXL memory comprises a second port, wherein the first CXL memory is connected to the second CXL switch through the first port, and wherein the second CXL memory is connected to the second CXL switch through the second port.
Bert teaches the computing system comprising wherein the memory device (Fig. 1, Memory sub-system 110 comprising first and second CXL memory devices 130 and 140) comprising a first CXL memory and a second CXL memory (Fig. 1, First and second CXL memory devices 130/140 and Fig. 4, first and second CXL memory devices 420-1/420-2 are the same embodiment; Paragraph 0056, FIG. 4 is a block diagram of a visibility configuration of a system 400 that can implement node coherency for storage related data, in accordance with some embodiments of the present disclosure… Paragraph 0060, Each of the memory devices includes a number of volumes, with each of the volumes including a port… each port can correspond to the interface standard (e.g., PCIe or CXL)), wherein the first CXL memory comprises a first port (Fig. 4, First port 421-1 of device 420-1), wherein the second CXL memory comprises a second port (Fig. 4, Second port 421-2 of device 420-2), wherein the first CXL memory is connected to the second CXL switch through the first port (Fig. 4, Device 420-1 (i.e. first CXL memory) connected to switch domain 430-2 (i.e. second CXL switch) via port 421-1 (i.e. first port)), and wherein the second CXL memory is connected to the second CXL switch through the second port (Fig. 4, Device 420-2 (i.e. second CXL memory) connected to switch domain 430-2 (i.e. second CXL switch) via port 421-2 (i.e. second port)).
Hahn, Wang, and Bert are analogous arts because they are in the same field of endeavor of switching between external host/servers and storage devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hahn/Wang’s computing system to incorporate the teachings of Bert and include multiple CXL memory devices coupled to the second switch of Hahn.
One of ordinary skill in the art would be motivated to make the modifications in order to provide redundancy during system failure using fast storage memory types while reducing costs (See Bert: Paragraphs 0015-0017 and 0019-0020).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hahn (US 2023/0176744) in view of Wang (US 2019/0235777) and further in view of Bradshaw (US 2021/0081325).
Regarding claim 15, Hahn in view of Wang teaches the operating method of claim 14.
Hahn teaches the operating method comprising: after receiving the second read request and the fourth read request (Fig. 6, L2P table read requests are sent to the memory device (Fig. 3, Controller unit 322) by the data storage devices 306 a/b in step 604 via port 310 and DRAM HMB controller 326 (i.e. second switch) in Figure 3).
Neither Hahn nor Wang teaches the operating method comprising: scheduling the fourth read request based on pre-determined priorities so that the fourth read request is processed prior to the second read request.
Bradshaw teaches the operating method comprising: scheduling the fourth read request based on pre-determined priorities so that the fourth read request is processed prior to the second read request (Fig. 3, NVRAM 306 and NAND 308 are associated with different priorities based on memory type/speed and different requests are scheduled based on device priorities; Paragraph 0100, a faster memory device type is selected for use with the determined priority. Processing device 310 uses metadata 320, 322 to select an address range that physically stores data in a memory device of the selected faster memory device type).
Hahn, Wang, and Bradshaw are analogous arts because they are in the same field of endeavor of managing data transfers to memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hahn/Wang’s operating method to incorporate the teachings of Bradshaw and include address range allocations for different memory types based on a priority of a memory type.
One of ordinary skill in the art would be motivated to make the modifications in order to allocate address ranges based on appropriate memory latencies, thus enabling the computing system to adequately support heterogeneous memory types efficiently (See Bradshaw: Paragraphs 0032, 0033, and 0039).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hahn (US 2023/0176744) in view of Wang (US 2019/0235777) in view of Malwankar (US 2014/0289462) and further in view of Bradshaw (US 2021/0081325).
Regarding claim 18, Hahn in view of Wang teaches the operating method of claim 12. Neither Hahn nor Wang teaches the operating method further comprising: in an initialization operation, sending, by the first storage device to the memory device, a first memory allocation request including first characteristic information indicating a type or important of data stored in the first storage device; in the initialization operation, sending, by the second storage device to the memory device, a second memory allocation request indicating a type or importance of data stored in the second storage device; and determining, by the memory device, priorities of the first storage device and the second storage device based on the first characteristic information and the second characteristic information.
Malwankar teaches the operating method further comprising: in an initialization operation, sending, by the first storage device to the memory device, a first memory allocation request including first characteristic information indicating a type or important of data stored in the first storage device (Fig. 3, Device discovery during power up operation discovers health of the data (i.e. health-type); Paragraph 0032, when the disk array 104 powers up, the processor 302 may send a discovery request to identify the different devices associated with the disk array 104… processor 302 may have information regarding the number of storage devices 308a-n such as the total storage space associated with the number of storage devices 308a-n, health of each storage device); in the initialization operation, sending, by the second storage device to the memory device, a second memory allocation request indicating a type or importance of data stored in the second storage device (Fig. 3, Device discovery is performed for the multiple storage arrays).
Hahn, Wang, and Malwankar are analogous arts because they are in the same field of endeavor of managing data transfer for memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hahn/Wang’s operating method to incorporate the teachings of Malwankar and enable the creation of separate memory mapping tables during an initialization operation of the computing system based on health-type.
One of ordinary skill in the art would be motivated to make the modifications in order to reduce delays and latency of performing data transfer operations (See Malwankar: Paragraphs 0002 and 0003).
The combination of Hahn/Wang/Malwankar does not teach the operating method comprising determining, by the memory device, priorities of the first storage device and the second storage device based on the first characteristic information and the second characteristic information.
Bradshaw teaches the operating method comprising determining, by the memory device, priorities of the first storage device and the second storage device based on the first characteristic information and the second characteristic information (Fig. 3, NVRAM 306 and NAND 308 are associated with different priorities based on memory type/speed and have associated address ranges 324/326 based on memory type; Paragraph 0100, a faster memory device type is selected for use with the determined priority. Processing device 310 uses metadata 320, 322 to select an address range that physically stores data in a memory device of the selected faster memory device type).
Hahn, Wang, Malwankar, and Bradshaw are analogous arts because they are in the same field of endeavor of managing data transfer for memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hahn/Wang/Malwankar’s operating method to incorporate the teachings of Bradshaw and include address range allocations for different memory types based on a priority of a memory type.
One of ordinary skill in the art would be motivated to make the modifications in order to allocate address ranges based on appropriate memory latencies, thus enabling the computing system to adequately support heterogeneous memory types efficiently (See Bradshaw: Paragraphs 0032, 0033, and 0039).
Allowable Subject Matter
Claims 6-9 and 11 would be allowable if rewritten to overcome the rejections under Double Patenting, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims, and if the Claim Objections are overcome.
Claims 16-17 would be allowable if rewritten to overcome the rejections under Double Patenting, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2018/0052694 to Lee discloses that a root complex performs arbitration between interconnected system modules (See Lee: Paragraph 0055, The root complex 2005 may arbitrate communication between the main processor 2100, the working memory 2200, and the endpoint devices 2400a, 2500, and 2600).
US PGPUB 2009/0327645 to Doi discloses serially connected switches coupled in a hierarchical fashion (See Doi: Figure 1, Switches 90a/b and 50).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY Z WANG whose telephone number is (571)270-1716. The examiner can normally be reached 9 am - 3 pm (Monday-Friday).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
Prosecution Insights