Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1,2,5-7,10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3,7,8,9,12 of U.S. Patent No. 12292827. Although the claims at issue are not identical, they are not patentably distinct from each other because although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1-3,7,8,9,12 of U.S. Patent No. 12292827 contain every element of claims 1,2,5-7,10 of the instant application and thus anticipate the claims of the instant application. Therefore the claims of the instant application are not patentably distinct from the earlier patent claims and as such are unpatentable.
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,3 of U.S. Patent No. 12292827. Although the claims at issue are not identical, they are not patentably distinct from each other because although claim 20 is directed to a method claim it would be obvious to one of ordinary skill in the art to have the storage device of claim 1 execute the method steps.
Claims 1,20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13,17 of U.S. Patent No. 12292827 in view of Choi (USPN 20200310987A1).
Claims 13,17 of the 12292827 patent discloses all limitations of the instant applications claims 1,20 except for logical addresses and physical addresses.
Choi discloses logical addresses and physical addresses in a map table in paragraph 0012.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have logical addresses and physical addresses in a map table because a map table stores mapping information as disclosed in paragraph 0025.
Although the claims at issue are not identical, they are not patentably distinct from each other because although claim 20 is directed to a method claim it would be obvious to one of ordinary skill in the art to have the storage device of claims 13,17 execute the method steps.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hashimoto (USPN 20120246388A1).
As per claim 11, Hashimoto discloses a storage device comprising: a nonvolatile memory device comprising a plurality of memory cells (paragraph 0087 - The NAND flash memory 13 includes (n+1) NAND memory chips Chip0 to Chipn, where n is an integer of 0 or more. The NAND memory chips Chip0 to Chipn may be configured to be able to operate in parallel. Each NAND memory chip comprises a memory cell array including a plurality of flash memory cells and peripheral circuits (for example, a row decoder, a column decoder, a page buffer, and a data cache). The memory cell array of the NAND flash memory 13 includes a plurality of blocks. Each block includes a plurality of pages. A block is the minimum unit of data erase. A page is the minimum unit of data write/read.); and
a controller (paragraph 0086 - The SSD controller 11 controls various kinds of operations of the entire SSD 3. The SSD controller 11 reads a program stored in the NAND flash memory 13 to the DRAM 12 and executes predetermined processing to create various kinds of tables on the DRAM 12. The SSD controller 11 also receives a write instruction, a read instruction, an erase instruction, and the like from the host apparatus 2, and executes predetermined processing for the NAND flash memory 13 in response to these instructions.) configured to:
receive a read request from an external host device, wherein the read request corresponds to a first zone from among a plurality of zones corresponding to the plurality of memory cells (paragraph 0124 - The SSD 3 receives a read instruction from the host apparatus 2 (step S50). The read instruction includes a read command and a logical address.),
based on receiving the read request, determine whether a zone read service is active for the first zone, wherein the zone read service is based on a zone map table corresponding to the plurality of zones (paragraph 0125 - The SSD controller 11 reads the active block table from the DRAM 12 (step S51). The SSD controller 11 refers to a physical block ID corresponding to the logical address received from the host apparatus 2 (step S52). – zone is the locations of the block in a particular chip),
based on determining that the zone read service is active for the first zone, obtain read data corresponding to the read request based on a logical address included in the read request and the zone map table, and provide the read data to the external host device (paragraph 0125 - If the physical block ID exists in the active block table, the SSD controller 11 executes written area read processing from then on (device-valid data read operation). That is, the SSD controller 11 reads the active page table (step S53), and reads a corresponding page from the NAND flash memory 13 (step S54). The SSD controller 11 sends the read data to the host apparatus 2 (step S55).).
Claims 3,4,8,9,12-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1-10,20 are not rejected under a prior art rejection based on the inclusion of the following limitations ‘based on the first zone being full, activate a zone read service for the first zone, wherein the zone read service is based on a zone map table corresponding to the plurality of zones, and based on the zone read service being activated for the first zone, process read requests for the first zone from the external host device using the zone map table’ not being found in the closest prior art. The closest prior art of 20240094903 only discloses that data can be read from a zone from when it is full but not any activation of a read service.
The closest prior art USPN 20240094903 - [0032] Once the zone is full (e.g., no further host data can be written to that active zone), or if the host does not intend to write data further to that zone (e.g., even if the zone is only partially full), the host may send a zone finish command to the flash storage device indicating to close the active zone or otherwise change its status to an inactive zone. In response to the zone finish command, the flash storage device may remove the zone from the list of active zones and may not accept any more zone write commands to that zone. However, since the host may still issue zone read commands to read data from that zone, the flash storage device continues to maintain the L2P mapping table with the previous L2P mapping entries for each logical address in that newly inactive zone. Later on, if the host determines to re-use the zone (e.g., for a different application), the host may issue a zone reset command to the flash storage device indicating to reset the zone. In response to the zone reset command, the flash storage device may remove the L2P mapping entries associated with that zone, and may afterwards write new host data to that zone with associated L2P mapping entries in response to a subsequent zone open/zone write commands.;
USPN 20220137817 - [0071] When pieces of data in all pages in a memory block corresponding to an open zone are completely programmed, the memory system switches the open zone to a closed zone, and then switches the closed zone to a full zone. Such a full zone (FULL) denotes a zone in which no empty area is present in the corresponding memory block. When an application provides an erase command for the full zone or the active zones to the memory system, the memory system performs an erase operation on the memory block corresponding to the zone for the erase command, and thereafter switches the zone to an empty zone. The empty zone (EMPTY) denotes a zone in which the corresponding memory block is an empty memory block.
[0075] The HIL 211 of the data processor 210 may perform operations related to communication between the memory controller 200 and the host 50. In some implementations, the HIL 211 may receive a write request or a read request from the host 50. When a write request is received from the host 50, the HIL 211 may receive write data from the host 50. The received write data may be stored in the write buffer 231 of the memory component 230. The HIL 211 may transfer read data to the host 50 in response to a read request.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Yolanda L Wilson whose telephone number is (571)272-3653. The examiner can normally be reached M-F (7:30 am - 4 pm).
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/Yolanda L Wilson/Primary Examiner, Art Unit 2113
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