DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 6-7, 10, 12-13, and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilson (US 20200117558 A1) in vew of Mauro (US 8499171 B2).
Regarding claim 1, Wison teaches an intelligent post package repair (PPR) method for a memory device wherein after fabrication and before placement into a chip package, memory device defects are repaired by utilizing fuses and anti-fuses (para. [0013]-[0017]). Wilson discloses:
A memory device (FIG. 3: memory device 305) comprising:
a memory array (FIG. 3: memory array 315);
a plurality of fuses (FIG. 3: fuse array 330);
Wilson also discloses the local memory controller 340 may be configured to disable any fuse bank 335 (para. [0081]). However, Wilson does not teach a disabling fuse and a control logic operatively coupled with the plurality of fuses and the disabling fuse to perform operations during manufacturing of the memory device, the operations comprising:
determining whether the plurality of fuses are programmed; and
responsive to determining that the plurality of fuses are programmed, blowing the disabling fuse to disable a blow functionality, wherein the blow functionality is triggered by a subsequent blow command to blow the plurality of fuses.
Mauro, in the same field of endeavor, teaches a security system and method wherein, “To ensure that a provisioned hardware key cannot be altered by blowing the remaining hardware key fuses, a disabling fuse 90d may be utilized. When the disabling fuse is blown, the programming functionality for the hardware key fuses may be disabled.” (emphasis added) (see para. [0060]).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the post packing repair (PPR) method of Wilson to also include a disabling fuse designed to disable the programming (blow) functionality of the fuses and anti-fuses as taught by Mauro. One of ordinary skill in the art would have been motivated to make this modification for the benefit of ensuring provisioned security features cannot be altered (Mauro at para. [0060]).
Claim 12 is a method claim corresponding with the subject matter recited in claim 1. Therefore, Wilson teaches the physical components and post-fabrication steps required to perform a PPR method utilizing fuses and anti-fuses; and Mauro teaches the required component, a disabling fuse, to disable the fuses or anti-fuses of the PPR method, as set forth in the obviousness rejection of claim 1 above.
Claim 17 is an apparatus claim corresponding with the subject matter recited in claim 1. Therefore, Wilson teaches the physical components (equivalent with a non-transitory computer-readable storage medium, i.e. a memory device) and post-fabrication steps required to perform a PPR method utilizing fuses and anti-fuses; and Mauro teaches the required component, a disabling fuse, to disable the fuses or anti-fuses of the PPR method, as set forth in the obviousness rejection of claim 1 above.
Regarding claims 2, 13, and 18, electronic fuses and anti-fuses are well-known in the art. Willson discloses a fuse array 330 comprising fuses and anti-fuses that are presumably electronic. Mauro discloses an e-fuse in para. [0048]. Therefore, it would have been an obvious matter to implement a disabling fuse as an electronic fuse or anti-fuse.
Regarding claim 6, Wilson discloses the plurality of fuses comprises one or more fuses that are programmed to repair one or more addresses of the memory device (Abstract; para. [0017]).
Regarding claim 7, Wilson discloses a PPR method utilizing fuses and anti-fuses occurring after silicon die fabrication and before packaging (para. [0013]). It would have been obvious to a person having ordinary skill in the art to blow a disabling fuse, as taught by Mauro, during a last step of manufacturing of the memory device because disabling fuses after they are configured after fabrication (at the end of manufacturing) is the only logical timeframe to perform said task. That is, it would have been common sense to a person having ordinary skill in the art.
Regarding claim 10, Wilson discloses receiving a command of a post package repair (PPR) function, wherein the PPR function is directed to one or more fuses of the plurality of fuses; and performing the PPR function on the one or more fuses of the plurality of fuses (Abstract; para. [0017]).
Allowable Subject Matter
Claims 3-5, 8-9, 11, 14-16, objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
