DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. 12281938. Although the claims at issue are not identical, they are not patentably distinct from each other because the inventive concept of a light detection substrate with plurality of pixels, a circuit substrate with plurality of MOS switch circuits, each pixel includes at least one APD, the APD has a light receiving region, a MOS switch circuit region with the MOS switch circuits overlaps the light receiving region and the area of the MOS switch circuit region is larger than the area of at least one light receiving region, the APD and MOS circuit switch are connected as described in the claims is taught by the present application and US patent 12281938.
In regards to claim 1, 12281938 teaches a light detection device (claim 1), comprising: a light detection substrate having a main surface and including a plurality of pixels disposed in a direction along the main surface (claim 1, lines 2-4); and a circuit substrate that includes a plurality of MOS switch circuits arranged in the direction along the main surface and electrically connected to corresponding pixels among the plurality of pixels (claim 1, lines 5-8), wherein: each of the pixels includes at least one avalanche photodiode configured to operate in a Geiger mode while individually forming a light receiving region, the at least one avalanche photodiode forms at least one light receiving region in a pixel area occupied by a corresponding pixel among the plurality of pixels, a MOS switch circuit region occupied by the MOS switch circuits overlaps with the at least one light receiving region formed in the pixel area when viewed from a direction perpendicular to the main surface, an area of the MOS switch circuit region is larger than an area of one of the at least one light receiving region formed in the pixel area, when viewed from the direction perpendicular to the main surface, and the at least one avalanche photodiode included in each of the pixels is connected to one of the MOS switch circuits (claim 1, lines 9-28).
Claims 2 to 25 are equivalents to claims 2-25 in 12281938.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kubota et al. (US 20200292675) teaches a substrate (20) with a plurality of switch circuits (SwR/XFR1 to XFRn) and a plurality of pixels (CU1 to CUm, CHU1 to CHUn) (fig. 4), each of the pixels in the plurality of pixels included a plurality of APDs (APD) (fig. 3), the plurality of avalanche photodiodes (APD) included in each of the pixels is electrically connected in parallel to each other and is each connected to one of the MOS switch circuits (XFR) (see fig. 3, 4 and 5), where an area of the plurality of MOS switch circuits (XFR) is larger than one light receiving region of at least one of the plurality of APDS (DC) (see fig. 2), the MOS switch region does not overlap the APD light receiving region (paragraph 48), but does not specifically teach two substrates as claimed and the overlapping of the APDs and switch circuit regions.
Kubota et al. (US 20200300985) teaches a plurality of pixels (12) each pixel with a plurality of APDs (paragraph 29), a plurality of switch circuits (111, 112, 113) connected to each pixel (12), but does not specifically teach two substrates as claimed, the overlapping of the APDs and switch circuit regions and the specific area of the switch circuit region as compared to the APDs and pixel areas.
Ota (US 20180270405) teaches a plurality of pixels (12) each with a plurality of avalanche photodiodes (APD1, APD2, APD3) and a switch circuit (Sw1, Sw2, Sw3) (see fig. 2 and 9), the avalanche photodiodes (APD) are connected to the switch circuit (SW1, SW2, SW3) (see fig. 9), but does not specifically teach two substrates as claimed and the specific area of the switch circuit region as compared to the APDs and pixel areas.
Iwata (US 20210043792) teaches a light detection substrate having a main surface and including a plurality of pixels (101) disposed in a direction along the main surface (substrate 11/301); and a circuit substrate (21/401) that includes a plurality of MOS transistor circuits (425/quench circuit, paragraph 56) arranged in the direction along the main surface and electrically connected to corresponding pixels among the plurality of pixels (see fig. 1, 2 and 3), wherein: each of the pixels (101) includes at least one avalanche photodiode (201) configured to operate in a Geiger mode while individually forming a light receiving region (paragraph 34), the at least one avalanche photodiode forms at least one light receiving region (325/322/321) in a pixel area occupied by a corresponding pixel among the plurality of pixels (see fig. 1, 2 and 3), a MOS transistor circuit region (region with all of the transistor circuits 425, fig. 1, 2 and 3) occupied by the MOS transistor circuits (425) overlaps with the at least one light receiving region (325/322/321) formed in the pixel area when viewed from a direction perpendicular to the main surface, an area of the MOS transistor circuit region is larger than an area of one of the at least one light receiving region formed in the pixel area, when viewed from the direction perpendicular to the main surface, and the at least one avalanche photodiode included in each of the pixels is connected to one of the MOS transistor circuits (fig. 1, 2 and 3), but does not specifically teach MOS switch circuits, the MOS transistor is a quench structure, not switching.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER D BENNETT whose telephone number is (571)270-3419. The examiner can normally be reached 9AM-6PM EST M-F.
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/JENNIFER D BENNETT/Examiner, Art Unit 2878
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