DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the synchronization circuit, as recited in Claims 8 and 12, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the first signal" in line 2. There is insufficient antecedent basis for this limitation in the claim. Furthermore, it is unclear this limitation is referring to previously recited the first clock signal in independent Claim 1, or introducing a new first signal. For examination purposes and advance the prosecution of the present patent application, examiner has interpreted “the first signal” to read “the clock first signal” (i.e. they are the same). Appropriate correction and/or clarification is required.
Claim 11 recites the limitation "the first signal" in line 2. There is insufficient antecedent basis for this limitation in the claim. Furthermore, it is unclear this limitation is referring to previously recited the first clock signal in independent Claim 10, or introducing a new first signal. For examination purposes and advance the prosecution of the present patent application, examiner has interpreted “the first signal” to read “the clock first signal” (i.e. they are the same). Appropriate correction and/or clarification is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-11 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hardesty et al. (US 5,963,068; hereinafter referred to as Hardesty).
With regard to Claims 1 and 10, Hardesty discloses in Figs. 3-4 an electronic device an associated method of generating an output clock signal, comprising a first electronic circuit (310, 320, 350) configured to generate a first clock signal (PLL clock) and a second signal (PHASE LOCK) indicating a state of stability of a frequency of the first clock signal (PLL clock), the second signal having a first value during a first period (t0 -t1) from a starting of the first electronic circuit and a second value after the first period (as depicted in Fig. 4); and a second electronic circuit (330, 340) configured to generate an output clock signal (SYSTEM CLOCK) having a frequency equal to the frequency of the first clock signal divided by a first factor (M is a first factor n) when the second signal is at the first value (between t1-t2) and having the frequency of the first clock signal (PLL clock), or a frequency equal to the frequency of the first clock signal (PLL clock) divided by a second factor (M is a second factor, that is another factor n, which is smaller than the first factor), as a consequence of a change of the second signal to the second value (see column 4, lines 42-47 and in conjunction with Fig. 4).
With regard to Claims 2 and 11, as best understood, wherein the second electronic circuit (330, 340) is configured to generate the output clock signal (SYSTEM CLOCK) having a frequency equal to the frequency of the first clock signal (PLL clock) divided by the second factor, from the time of the edge of the first clock signal following the change of the second signal (PHASE LOCK) to the second value (see column 4, lines 42-47 and in conjunction with Fig. 4).
With regard to Claim 3, wherein the first electronic circuit comprises a phase-locked loop (310) configured to generate the first clock signal and the second signal (as depicted in Fig. 3)
With regard to Claim 4, wherein the second electronic circuit comprises a frequency divider (330) configured to perform the division of the frequency of the first clock signal (PLL clock).
With regard to Claim 5, wherein the second electronic circuit inherently comprises a multiplexer (340) having an output coupled to a divider control input of the frequency divider (340), a first input configured to receive the first factor and a second input configured to receive the second factor, the multiplexer being configured to transmit the first factor when the second signal is at the first value and to transmit the second factor when the second signal is at the second value (see column 3, line 34 through column 4, line 47). Note that the frequency divider 330 also can function as a multiplexer that allows multiple input signals (a plurality of different factors of M={1,n} ) to share a single output line by selecting one input signal at a time based on control signal (SELECT signal in Fig. 3). Therefore, the limitation such as “the second electronic circuit inherently comprises a multiplexer” is also anticipated by the above cited reference.
With regard to Claim 6, wherein the second electronic circuit (330, 340) comprises a first frequency divider having a divider control input configured to receive the first factor and configured to perform the division of the frequency of the first clock signal by the first factor (M is a first factor n); and a second frequency divider having a divider control input configured to receive the second factor and configured to perform the division of the frequency of the first clock signal by the second factor (M is a second factor, that is another factor n, which is smaller than the first factor).
With regard to Claims 9 and 13, wherein the first factor is an integer greater than or equal to two. Note that Hardesty discloses that “When the SELECT signal is generated, divider 330 switches to produce a SYSTEM CLOCK at the full frequency of the PLL CLOCK (or some fraction thereof as desired).” (emphasis added) see column 3, lines 64-67. In other words, the first factor can be set at an integer greater than or equal to two. Therefore, this claim is also anticipated by the above cited reference.
Allowable Subject Matter
Claims 7, 8 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reference of Note
The prior art of Record and not relied upon is considered pertinent to applicant’s disclosure:
Moehlman (US 10,788,233) teaches a Phase Locked Loop (PLL) lock detection includes a lock signal is determined in response to the phase error being less than an upper phase threshold and greater than a lower phase threshold, and the frequency error being less than an upper frequency threshold and greater than a lower frequency threshold.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAI L NGUYEN whose telephone number is (571)272-1747. The examiner can normally be reached Monday-Friday from 09:00am to 06:00pm Eastern time.
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/HAI L NGUYEN/Primary Examiner, Art Unit 2836 July 31, 2026
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