Prosecution Insights
Last updated: July 17, 2026
Application No. 19/084,159

METHOD AND DEVICE FOR BACKEND WEAR LEVEL BALANCING OF SEPARATED STORAGE DOMAINS

Non-Final OA §103
Filed
Mar 19, 2025
Priority
Apr 23, 2024 — provisional 63/637,643 +1 more
Examiner
DOAN, KHOA D
Art Unit
2133
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
323 granted / 360 resolved
+34.7% vs TC avg
Moderate +8% lift
Without
With
+7.9%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
10 currently pending
Career history
371
Total Applications
across all art units

Statute-Specific Performance

§101
4.7%
-35.3% vs TC avg
§103
72.5%
+32.5% vs TC avg
§102
5.5%
-34.5% vs TC avg
§112
10.9%
-29.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 360 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno et al (U.S. 11,086,775)), and in view of Prakash et al (U.S. 2024/0354257). Regarding claim 1: A method comprising: receiving a command at a controller of a storage device, wherein a logical capacity of the storage device is split into domains; Kanno discloses, Fig. 1, storage device 3 comprises controller 4, memory 5 is logically divided into a plurality of namespaces (domain), each namespace functions as one area in the memory 5 (NS0-NSM). determining, by the controller, a logical address associated with the command, wherein the logical address is associated with a first domain of the storage device; Fig. 10, controller 4 (reception unit 13 receives a read command including namespace identifier NSID 6R, logical address LBA 7R from host 2 (Fig. 10), 12:25-55. Kanno further discloses wear leveling can be performed between the namespaces NS0 to NSM. The assignment change between the namespaces NS0 to NSM and the blocks B S0 to BSM may be performed by the configuration unit 14 observing the data storage conditions of the namespaces NS0 to NSM based on an observation result as in the time of generation of the management data 18, and the namespace to be assigned to the block can be changed, the wear leveling can be performed between the namespaces NS0 to NSM, and the life of the nonvolatile memory 5 can be prolonged (4:30-50, 7:10-20). Prakash discloses when information is migrated from one memory location to another (i.e., when “memory is migrated”), the memory storage locations of the information are changed without changing the virtual addresses of the information. After migration, the information may be accessed by changing the mapping for the virtual addresses from mapping to old physical memory addresses, corresponding to the old storage locations, to mapping to new physical memory addresses corresponding to the new storage locations. In this manner, the physical memory locations at which information is stored may be changed while the virtual addresses of the information appear the same to an application or input-output (IO) device seeking to access the information (¶002). Prakash further discloses the technique to avoid page fault when a read command is received prior to completion of moving data to the new location. Prakash, ¶0028-¶029, command is redirected to new physical address corresponds to logical address included in the read command. Kanno discloses the wear leveling can be done between namespaces (domains). Each of the namespace is associated with a dedicate address translation table (controller resources) T0-YM to provides LBA to PBA translation (3:35-40). The address translation table is updated when data in a corresponding namespace is changed/updated (5:30-45, 7:25-35, and Fig. 4). It is well-known that data is migrated/transferred from a high wear count block to a lesser wear count block, and a management or mapping table is updated to reflect the changes. Prakash discloses the idea of redirecting read command, from an old target physical address, to a new target physical address corresponds to the same logical address received from the read command. One ordinary skill in the art, at the time the invention was filed, would be able to combine the Kanno and Prakash disclosures to perform wear leveling between namespace to improve the memory life. In response to a read command with a logical address associated with an old physical address, after the wear leveling procedure, it is obvious to one skill of the art to consider redirect the command to the new physical address to read valid data. Both of Kanno and Prakash are analogous in the field of memory management, mapping. Thus, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the disclosures of Prakash and Kanno to consider rerouting the command from first resources of the controller attributed to the first domain to second resources of the controller attributed to a second domain of the storage device, based on a physical address associated with the logical address. The motivation for doing so is to apply a known technique, of Prakash, to the method/apparatus ready for improvement of Kanno, to yield predictable result. Regarding claim 13: The method of claim 1, wherein: the first resources comprise first hardware and firmware resources dedicated to the first domain, and the second resources comprise separate second hardware and firmware resources dedicated to the second domain; or the first resources and the second resources comprise hardware and firmware resources used on a rotating basis between the first domain and the second domain. Kanno, Fig. 1, dedicated buffer memory F0-FM, and address translation table L0-LM each corresponds to a namespace NS0-NSM. Regarding claim 14: A storage device, comprising: a controller; and a non-transitory computer readable storage medium having a logical capacity split into domains and storing instructions that, when executed, cause the controller to: receive a command; determine a logical address associated with the command, wherein the logical address is associated with a first domain; Kanno discloses, Fig. 1, storage device 3 comprises controller 4, memory 5 is logically divided into a plurality of namespaces (domain), each namespace functions as one area in the memory 5 (NS0-NSM). Fig. 10, controller 4 (reception unit 13 receives a read command including namespace identifier NSID 6R, logical address LBA 7R from host 2 (Fig. 10), 12:25-55. Kanno further discloses wear leveling can be performed between the namespaces NS0 to NSM. The assignment change between the namespaces NS0 to NSM and the blocks B S0 to BSM may be performed by the configuration unit 14 observing the data storage conditions of the namespaces NS0 to NSM based on an observation result as in the time of generation of the management data 18, and the namespace to be assigned to the block can be changed, the wear leveling can be performed between the namespaces NS0 to NSM, and the life of the nonvolatile memory 5 can be prolonged (4:30-50, 7:10-20). Prakash discloses when information is migrated from one memory location to another (i.e., when “memory is migrated”), the memory storage locations of the information are changed without changing the virtual addresses of the information. After migration, the information may be accessed by changing the mapping for the virtual addresses from mapping to old physical memory addresses, corresponding to the old storage locations, to mapping to new physical memory addresses corresponding to the new storage locations. In this manner, the physical memory locations at which information is stored may be changed while the virtual addresses of the information appear the same to an application or input-output (IO) device seeking to access the information (¶002). Prakash further discloses the technique to avoid page fault when a read command is received prior to completion of moving data to the new location. Prakash, ¶0028-¶029, command is redirected to new physical address corresponds to logical address included in the read command. Kanno discloses the wear leveling can be done between namespaces (domains). Each of the namespace is associated with a dedicate address translation table (controller resources) T0-YM to provides LBA to PBA translation (3:35-40). The address translation table is updated when data in a corresponding namespace is changed/updated (5:30-45, 7:25-35, and Fig. 4). It is well-known that data is migrated/transferred from a high wear count block to a lesser wear count block, and a management or mapping table is updated to reflect the changes. Prakash discloses the idea of redirecting read command, from an old target physical address, to a new target physical address corresponds to the same logical address received from the read command. One ordinary skill in the art, at the time the invention was filed, would be able to combine the Kanno and Prakash disclosures to perform wear leveling between namespace to improve the memory life. In response to a read command with a logical address associated with an old physical address, after the wear leveling procedure, it is obvious to one skill of the art to consider redirect the command to the new physical address to read valid data. Both of Kanno and Prakash are analogous in the field of memory management, mapping. Thus, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the disclosures of Prakash and Kanno to consider reroute the command from first resources of the controller attributed to the first domain to second resources of the controller attributed to a second domain, based on a physical address associated with the logical address. The motivation for doing so is to apply a known technique, of Prakash, to the method/apparatus ready for improvement of Kanno, to yield predictable result. Allowable Subject Matter Claims 2-12, 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Camp et al (U.S. 9,389,792) discloses a technique to relocate data from a first physical location to a second physical location, and services a read request using old data at the first physical address, until the data is fully committed to the second physical location. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHOA D DOAN whose telephone number is (571)272-5950. The examiner can normally be reached Mon-Fri 1000-1700. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ROCIO DEL MAR PEREZ-VELEZ can be reached at 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHOA D DOAN/Primary Examiner, Art Unit 2133
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Prosecution Timeline

Mar 19, 2025
Application Filed
Jun 10, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
98%
With Interview (+7.9%)
2y 0m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 360 resolved cases by this examiner. Grant probability derived from career allowance rate.

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