Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 6, 7, 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Collins (Unites Staes Patent 6158000), hereinafter Collins, in view of Stewart et al. (PGPUB 2016/03000064), Stewart.
Regarding claim 1, Collins teaches at least one processor; and a memory coupled to the at least one processor (FIG. 2 “CPU0-3 110-113” “MAIN MEMORY 115” “BIOS ROM 124” “PROCESSOR BUS 114” “PRIMARY EXP. BUS 1” “SECONDARY EXP. B”), wherein the at least one processor is configured to cause the system to: perform, by a first processor thread of a processor of the at least one processor, wake-up task operations and quick boot notification operations for a subsystem associated with the memory; perform, by a second processor thread of the processor, the memory restoration operation on the memory in parallel with one or more of the wake-up task operations or quick boot notification operations ([Col. 8 Lines 29-31] “interrupt vector that points to an entry point in the BIOS routine for performing the memory test. While the AP begins performing the memory test, the ESP continues with other POST tasks in step 328 before entering a wait loop 330.” FIG. 3 332-336. As one of processors is determined to be a bootstrap processor BSP, other processors are determined to be application processors. As shown in FIG. 3, when a power-on event or a remote wake-up packet occurs, some tasks of BSP and AP for a boot process are executed in parallel. As shown in FIG. 3 332-336, the memory is tested and cleared by the AP, which is an initialization process of the memory, while BSP execute other booting process, such as FIG. 3 “318-320”); and
perform run time initialization operations for the subsystem based on completion of the one or more of the wake-up task operations or quick boot notification operation ([Col. 8 Lines 32-34] “the ESP checks to see if the memory task is completed, and if so, the ESP proceeds to step 322 to do a summary report of the POST and memory test results.” FIG. 3 “318, 320, 324 LOAD/RUN OS”).
However, Collins does not teach a system-on-chip (SoC); interrupt a direct memory access engine to perform a memory restoration operation on a memory associated with the direct memory access engine.
Stewart teaches a system-on-chip (SoC) ([0015] “The hardware components of the SoC 100”); interrupt a direct memory access engine to perform a memory restoration operation on a memory associated with the direct memory access engine ([0020] “the SCPU 130 further includes a write-only direct memory access (DMA engine 156 configured to transfer data into the CC-RAM 154 from main memory (e.g., memories 118, 129).”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Collins by incorporating the teaching of Stewart of a system-on-chip (SoC); interrupt a direct memory access engine to perform a memory restoration operation on a memory associated with the direct memory access engine. They are all directed to initialization of a computer system. As well known in the art before the effective filing date of the claimed invention, the DMA engine can offload data movement tasks from a processor to improve data movement speed and CPU performance. Furthermore, the system-on-chip can improve power consumption and performance by reducing interconnects between components as various components are integrated onto a chip. Therefore, it would be advantageous to incorporate the teaching of Stewart of a system-on-chip (SoC); interrupt a direct memory access engine to perform a memory restoration operation on a memory associated with the direct memory access engine in order to improve performance and power consumption.
Regarding claim 3, Collins in view of Stewart teaches all the limitations of the SoC of claim 1, as discussed above.
Stewart further teaches wherein the processor includes the direct memory access engine, and the direct memory access engine is configured to control operations of the memory, and wherein the memory does not have a dedicated memory controller (FIG. 1, “SCPU 130” “CC-ROM 152” “CC-RAM 154” “DMA 156” [0020] “the SCPU 130 further includes a write-only direct memory access (DMA) engine 156 configured to transfer data into the CC-RAM 154 from main memory (e.g., memories 118, 120).” DMA is included in the SCPU. Access to CC-RAM is controlled by the DMA. Furthermore, Stewart suggests that as the DMA controls operation of the CC-RAM, the CC-RAM does not have a dedicated memory controller.).
Regarding claim 4, Collins in view of Stewart teaches all the limitations of the SoC of claim 3, as discussed above.
Collins, as modified above, further teaches wherein the first and second processor threads are part of the same core or different cores of the processor ([Col. 6 Lines 37-40] “multiple processor systems similar to system 100, one processor 113 is designated as the bootstrap processor (ESP), and the remaining processors 110–112 assume the role of application processors (AP).”).
Regarding claim 6, Collins in view of Stewart teaches all the limitations of the SoC of claim 1, as discussed above.
Stewart further teaches wherein the subsystem is a digital signal processor ([0016] “The ACPU 112 thus may comprises…a digital signal processor…”).
Regarding claim 7, Collins in view of Stewart teaches all the limitations of the SoC of claim 6, as discussed above.
Collins, as modified above, further teaches wherein the subsystem is an audio system, a safety system, a modem, a compute subsystem, a wireless communication subsystem, a neural signal processor (NSP) subsystem, or a sensor subsystem (FIG. 2 [Col. 5] Lines 10-13 “graphics accelerators, video systems 125, sound cards, network interfaces, and external bus interfaces such as SCSI and IEEE 1394.”).
Regarding claim 10, Collins in view of Stewart teaches all the limitations of the SoC of claim 1, as discussed above.
Stewart teaches wherein the at least one processor is further configured to cause the SoC to: enter, prior to the interruption of the direct memory access engine, a deep sleep mode, a suspend to random access memory (RAM) (STR) state, or another sleep state where the memory is powered down; determine a wake-up indication for the subsystem; and perform a quick boot operation for the subsystem responsive to the wake-up indication ([0022] “The method 200 initiates at block 202 with the deassertion of system reset for the host system implementing the SoC 100 (referred to herein as a "cold boot") or with the return of the SoC 100 from a suspended state (referred to herein as a "warm boot"), such as in response to detection of a Suspend-to-Ram (STR) wakeup event that returns the SoC 100 from a STR idle state. Following the reset, the SBC 102 assumes control of the SoC 100… As the OTP memory 104 stores the provisioning information 160 used by the SBC 102 to initialize the components of the SoC 100 during the boot process, at block 204 the SBC 102 waits for the OTP memory 104 to initialize following the system reset at block 202.” [0023] “executes the boot code from the CC-RAM 154 to boot the SoC 100 in accordance with the provisioning information 160 stored in the OTP memory 104.”).
Regarding claim 11, Collins in view of Stewart teaches all the limitations of the SoC of claim 1, as discussed above.
Collins, as modified above, further teaches wherein the at least one processor is further configured to cause the SoC to: restore, by the first processor thread of the processor, hardware components associated with the subsystem ([Col. 5 Lines 54-57] “Initialization of computer system 100 preferably includes performing a sequence of tasks. This task sequence may begin with causing every system component to enter an initial state at power-on.” [Col. 6 Lines 8-26]); and
initialize, by the first processor thread of the processor, one or more timers and interrupts associated with the subsystem ([Col. 6 Lines 24-28] “One implementation of the POST module preferably causes one of the processors to perform the following tasks:…a system timer test…”).
Regarding claim 12, Collins in view of Stewart teaches all the limitations of the SoC of claim 11, as discussed above.
Collins, as modified above, further teaches wherein the at least one processor is further configured to cause the system to: store, by the first processor thread of the processor, a start address and an address range of the memory to be cleaned, wherein the at least one processor is further configured to cause the SoC to interrupt the direct memory access engine includes (Col. 8 Line 2-20) to: send, by the first processor thread of the processor, a DM start message to the second processor thread and indicating the start address and the address range of the memory to be cleaned ([Col. 8 Lines 35-38] “The AP which receives the IPI message loads the interrupt vector into an instruction pointer register in step 332, retrieves the memory test routine in step 334, and performs a read/write test of the memory 115 in step 336.”).
Stewart teaches the SoC ([0015] “The hardware components of the SoC 100”).
Regarding claim 13, Collins in view of Stewart teaches all the limitations of the SoC of claim 1, as discussed above.
Collins, as modified above, further teaches wherein the at least one processor configured to cause the system to perform the wake-up task operations and the quick boot notification operations for the subsystem associated with the memory includes to: perform, by the first processor thread of the processor, the wake-up task operations; and perform, by the first processor thread of the processor, the quick boot notification operations responsive to completion of the wake-up task operations, wherein the run time initialization operations are performed responsive to completion of the quick boot notification operations (FIG. 3 318, 320, 322, 324).
Stewart teaches the SoC ([0015] “The hardware components of the SoC 100”).
Regarding claim 14, Collins in view of Stewart teaches all the limitations of the SoC of claim 14, as discussed above.
Collins, as modified above, further teaches to perform the run time initialization operations in parallel with the memory restoration operation (FIG. 3 318, 320, 322, 324, 332-340).
Regarding claim 15, Collins in view of Stewart teaches all the limitations of the SoC of claim 1, as discussed above.
Collins, as modified above, further teaches to transmit, by the first processor thread to the second processor thread, a direct memory poll request that requests a status of the memory restoration operation; and receive, by the first processor thread from the second processor thread, a direct memory poll request response indicating completion of the memory restoration operation (FIG. 3 340, 330, 322).
Regarding 16, Collins in view of Stewart teaches all the limitations of the SoC of claim 1, as discussed above.
Collins, as modified above, further teaches to start, by the first processor thread of the processor, a plurality of run time initialization processes for a plurality of run time initialization groups; perform, by one or more run time initialization threads, a corresponding run time initialization process for each run time initialization group of the plurality of run time initialization groups; and notify, by the one or more run time initialization threads, the processor upon completion of the run time initialization processes for each run time initialization group of the plurality of run time initialization groups (FIG. 3 316-322, 325-322, [Col. 5 Lines 54-57] “Initialization of computer system 100 preferably includes performing a sequence of tasks. This task sequence may begin with causing every system component to enter an initial state at power-on.” [Col. 6 Lines 8-26]); and
wherein the at least one processor is further configured to cause the SoC to: complete a quick boot operation responsive to receiving notifications for each run time initialization group of the plurality of run time initialization groups; and begin using the memory after completion of the quick boot operation (FIG. 3, 330, 322, 324).
Regarding 17, Collins in view of Stewart teaches all the limitations of the SoC of claim 16, as discussed above.
Collins, as modified above, further teaches wherein the SoC or the processor is not in a sleep state during the quick boot operation (FIG. 3 “304-320, 325-322” Since the processor is powered on and perform the booting process, the processor and the system is not in sleep state.).
Regarding claim 18, Collins in view of Stewart teaches all the limitations of the SoC of claim 16, as discussed above.
Collins, as modified above, further teaches wherein the wake-up tasks operations include restoring hardware and hardware configurations, and wherein the quick boot notification operations include notifying components of the subsystem or other subsystem via system message or interrupts (FIG. 3 316-322, 325-322, [Col. 5 Lines 54-57] “Initialization of computer system 100 preferably includes performing a sequence of tasks. This task sequence may begin with causing every system component to enter an initial state at power-on.” [Col. 6 Lines 8-26] FIG. 3 “314 SET UP SMI” [Col. 7 Lines 20-22] “SMIs are software-generated interrupts for various system management functions including interprocessor communication” [Col. 8 Lines 35-38] “The AP which receives the IPI message loads the interrupt vector into an instruction pointer register in step 332, retrieves the memory test routine in step 334, and performs a read/write test of the memory 115 in step 336.”).
Regarding claim(s) 19, the claim(s) 19 is the method claims of the apparatus claim(s) 1. The claim(s) 19 does(do) not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Collins in view of Stewart teaches all the limitations of the claim(s) 19.
Regarding claim 20, Collins teaches at least one processor; and a memory coupled to the at least one processor, wherein the at least one processor is configured to cause the system to: transmit, by a first processor thread of a processor of the at least one processor to a second processor thread of the processor, a direct memory start indication that indication ([Col. 8 Lines 20-26] “Returning to step 316, if a multiple processor environment is detected, then in step 325 the ESP may send an IPI to the other APs to have them conduct local tasks (e.g. tests of the processor registers and cache memory belonging to each AP). In step 326 the BSP instructs an AP to start performing the memory test.”);
perform, by the first processor thread, wake-up task operations for a subsystem associated with the memory; perform, by the first processor thread, quick boot notification operations for the subsystem ([Col. 6 Lines 24-36]; “One implementation of the POST module preferably causes one of the processors to perform the following tasks:” [Col. 6 Lines 47-53] “the ESP executes the above described POST tasks and additional tasks,…and cache memory belonging to each AP). The ESP concludes the POST process by executing the bootstrap loader to load and transfer control to the operating system.”);
transmit, by the first processor thread to the second processor thread, a direct memory poll request that requests a status of the memory restoration operation;
receive, by the first processor thread from the second processor thread, a direct memory poll request response indicating completion of the memory restoration operation; and perform run time initialization operations in parallel with the memory restoration operation ([Col. 8 Lines 38-47] “In step 338 the test results (i.e. passed or failed with failure details) are prepared for communication to the ESP, which in one implementation may be done by storing the results in a mailbox location for the ESP. In step 340 the AP signals task completion to the ESP and halts in step 342. In a preferred embodiment, the AP causes a system management interrupt (SMI) to be sent to the ESP to cause the ESP to check its mailbox location for memory test results.” [Col. 8 Lines 32-34] “the ESP checks to see if the memory task is completed, and if so, the ESP proceeds to step 322 to do a summary report of the POST and memory test results.”).
Stewart teaches a SoC ([0015] “The hardware components of the SoC 100”), a direct memory access engine to perform a memory restoration operation on a memory associated with the direct memory access engine ([0020] “the SCPU 130 further includes a write-only direct memory access (DMA engine 156 configured to transfer data into the CC-RAM 154 from main memory (e.g., memories 118, 129).”).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Collins in view of Stewart as applied to claim 1 above, and further in view of Banik et al. (United States Patent Application Publication US 2021/0089296), hereinafter Banik.
Regarding claim 2, Collins in view of Stewart teaches all the limitation of the SoC of claim 1, as discussed above.
However, Collins in view of Stewart does not teach wherein the memory includes layer 2 cache memory or vector tightly coupled memory (vTCM) for the processor.
Banik teaches wherein the memory includes layer 2 cache memory or vector tightly coupled memory (vTCM) for the processor ([0120] “the shared cache 1896a, 1896b may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Collins in view of Stewart by incorporating the teaching of Banik of L2 cache. They are all directed toward initialization process. As well known in the art before the effective filing date of the claimed invention, the L2 cache bridges a speed gap between L1 caches and RAM, which improves memory latency and improves performance by providing data when the processor cannot find data in L1. Therefore, it would be advantageous to incorporate the teaching of Banik of the L2 cache in order to improve performance of the system.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Collins in view of Stewart as applied to claim 1 above, and further in view of Peddle (United States Patent Application Publication US 2015/0355965), hereinafter Peddle.
Regarding claim 5, Collins in view of Stewart teaches all the limitations of the SoC of claim 1, as discussed above.
However, Collins in view of Stewart does not explicitly teach the memory restoration operation includes to: disable the memory by writing first control bits to the memory; enable error correction control (ECC) for the memory by writing control information to an ECCcontrol space of the memory; clean-up the memory by writing reset bits to the memory; and enable to memory by writing second control bits to the memory.
Peddle teaches the memory restoration operation includes to: disable the memory by writing first control bits to the memory; enable error correction control (ECC) for the memory by writing control information to an ECCcontrol space of the memory; clean-up the memory by writing reset bits to the memory; and enable to memory by writing second control bits to the memory (TABLE 1 “Bit 7 1 = Enable the ECC encoder when Preload B is loaded” “Bit 6 1 = Enable the ECC Decoder when Preload B is loaded” “Bit 5 0 = Clear the Flash Command Output Signal when Preload B is loaded” “Bit 4 0 = Clear the Flash Address Output Signal when Preload B is loaded” “Bit 2 1 = Enable Reads from the Flash when Preload B is loaded; 0 = Disable Reads from the Flash when Preload B is loaded” “Bit 1 1 = Enable Reads from the Flash when Preload B is loaded; 0 = Disable Reads from the Flash when Preload B is loaded”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Collins in view of Stewart by incorporating the teaching of Peddle of the memory restoration operation includes to: disable the memory by writing first control bits to the memory; enable error correction control (ECC) for the memory by writing control information to an ECCcontrol space of the memory; clean-up the memory by writing reset bits to the memory; and enable to memory by writing second control bits to the memory. It would be obvious to combine well known methods of the teaching of Collins in view of Stewart of initialization and the teaching of Peddle of controlling memory device.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Collins in view of Stewart as applied to claims 1 and 6 above, and further in view of LAN (United States Patent Application Publication US 2024/0070085), hereinafter LAN.
Regarding claim 8, Collins in view of Stewart teaches all the limitations of the SoC of claim 6, as discussed above.
Collins, as modified above, further teaches wherein the memory restoration operation includes one or more memory clean-up operations ([Col. 8 Lines 9-15] “a suitable memory test may include writing an alternating "1010 ... "bit pattern to that memory location, reading the stored value to verify that it is correct, writing the inverse alternating bit pattern "0101 . . . ", reading the stored value to verify that it is correct, and writing an all zero bit pattern "0000 . . . " to clear the memory location.”).
However, Collins in view of Stewart does not teach wherein the one or more memory clean-up operations include writing a bit value to each cache line of a plurality of cache lines.
LAN teaches wherein the one or more memory clean-up operations include writing a bit value to each cache line of a plurality of cache lines ([0045] “since the system has just been turned on or has just been woken up from a sleep mode, the cache memory controller 111 performs the first valid-bit-cleaning process to clean the valid bit of each index in the cache memory 130 one by one to be an invalid state. It should be noted that when the cache memory controller 111 performs the first valid-bit-cleaning process, the cache memory controller 111 may set the busy flag of the cache memory 130 to 1”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Collins in view of Stewart by incorporating the teaching of LAN of wherein the one or more memory clean-up operations include writing a bit value to each cache line of a plurality of cache lines. They are all directed toward initialization. As recognized by LAN, depending on the duration of the sleep mode and the environment in which the system is operating, the static random access memory that is utilized as a valid bit may still have some undischarged charge, leading to the contents of the cache memory being in a pseudo-valid state ([0006]). By clearing the cache memory, errors due to undischarged charge, leading to the contents of the cache memory being in a pseudo-valid state can be prevented. Therefore, it would be advantageous to incorporate the teaching of LAN of wherein the one or more memory clean-up operations include writing a bit value to each cache line of a plurality of cache lines in order to reduce errors.
Regarding 9, Collins in view of Stewart teaches all the limitations of the SoC of claim 1, as discussed above.
Collins, as modified above, further teaches wherein the memory restoration operation includes one or more memory initialization operations ([Col. 8 Lines 9-15] “a suitable memory test may include writing an alternating "1010 ... "bit pattern to that memory location, reading the stored value to verify that it is correct, writing the inverse alternating bit pattern "0101 . . . ", reading the stored value to verify that it is correct, and writing an all zero bit pattern "0000 . . . " to clear the memory location.”).
LAN teaches wherein the one or more memory clean-up operations include writing a bit value to each cache line of a plurality of cache lines ([0045] “since the system has just been turned on or has just been woken up from a sleep mode, the cache memory controller 111 performs the first valid-bit-cleaning process to clean the valid bit of each index in the cache memory 130 one by one to be an invalid state. It should be noted that when the cache memory controller 111 performs the first valid-bit-cleaning process, the cache memory controller 111 may set the busy flag of the cache memory 130 to 1”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
NARAYANA et al. (United States Patent Application Publication US 2019/0332425) teaches a SoC including a scheduler to schedule running of threads on one or more computing cores in a pre-boot environment.
Li et al. (United States Patent Application Publication US 2009/0083528) teaches to synchronize information between processors during system boot in a links-based multi-processor system.
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/HYUN SOO KIM/Examiner, Art Unit 2176
