Non-Final Rejection
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 21-22, 25-26, and 28 are rejected under 35 U.S.C. 102
Claims 1-20 are allowable
Claims 23-24 and 27 are objected to as containing allowable subject matter
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) filed on July 10th, 2025, has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-22 and 25-26 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Basu (U.S. Publication No. 2021/0055868 A1).
With regards to Claim 21, Basu teaches:
An operation of a memory controller comprising (Fig. 1; Paragraph 0031):
determining an importance level of level 1 or level 2 for data to read from a memory (Paragraphs 0046-0047 and 0049);
performing, for data with importance level 1, a first level read operation configured to obtain data with no errors or determine that data without errors cannot be obtained by a first read recovery operation (Paragraph 0025; Paragraphs 0049-0051);
and performing, for data with importance level 2, a second level read operation configured to terminate a second read recovery operation when a preset termination condition is satisfied (Paragraph 0025; Paragraphs 0049-0051).
With regards to Claim 22, Basu teaches the method of Claim 21 as cited above. Basu further teaches:
wherein the first level read operation comprises, a first read operation (Paragraphs 0049-0051; Paragraphs 0042-0043; Paragraphs 0036-0037);
and when the first read operation fails, the first read recovery operation configured to perform preset read recovery operations and be terminated when successful or after performing the preset read recovery operations, and wherein the second level read operation comprises, a second read operation (Paragraphs 0042-0043; Paragraph 0025; Paragraphs 0048-0051; Paragraphs 0036-0037; Paragraph 0087);
and when the second read operation fails, the second read recovery operation configured to perform preset read recovery operation and be terminated when successful or the preset termination condition is satisfied (Paragraphs 0042-0043; Paragraph 0025; Paragraphs 0048-0051; Paragraphs 0036-0037; Paragraph 0087).
With regards to Claim 25, Basu teaches the method of Claim 21 as cited above. Basu further teaches:
receiving a read command for composite data comprising a first bit unit including bits with the importance level I and a second bit unit including bits with the importance level 2 (Paragraphs 0047-0048, units and managed units in data to be corrected; Paragraphs 0019 and 0025 error in data read);
performing the first level read operation to read the first bit unit of the composite data (Paragraphs 0049-0051);
performing the second level read operation to read the second bit unit of the composite data (Paragraphs 0049-0051);
and transmitting a read failure message, composite data with no errors or composite data with an error, based on whether the first level read operation for the first bit unit is successful and whether the second level read operation for the second bit unit is successful (Paragraph 0025, successful vs unsuccessful; Paragraph 0052, host can use corrected data).
With regards to Claim 26, Basu teaches the method of Claim 21 as cited above. Basu further teaches:
receiving a read command for data comprising a first data block including the data with the importance level 1 and a second data block including the data with the importance level 2 (Paragraphs 0047-0048, units and managed units in data to be corrected; Paragraphs 0019 and 0025 error in data read);
reading the first data block by using the first level read operation (Paragraphs 0049-0051);
reading the second data block by using the second level read operation (Paragraphs 0049-0051);
and transmitting a read failure message, data with no errors or data with an error based on whether the first level read operation for the first data block is successful and whether the second level read operation for the second data block is successful (Paragraph 0025, successful vs unsuccessful; Paragraph 0052, host can use corrected data).
Claim 28 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cai et al. (U.S. Patent No. 10,901,656 B2), hereinafter referred to as Cai.
With regards to Claim 28, Cai teaches:
A storage device comprising (Fig. 2):
a memory configured to store data (Fig. 1-2; Col. 3, Line 64 – Col. 4, Line 15);
and a memory controller configured to receive a command from a first external device and control an operation of the memory based on the received command (Fig. 2; Col. 5, Lines 13-19),
wherein the memory controller comprises (Fig. 2),
a first interface configured to perform data communication with the first external device (Fig. 2; Col. 6, Lines 3-11);
a second interface configured to generate signal configured to control an operation of the memory (Fig. 2; Col. 6, Lines 12-22);
and at least one processor configured to (Col. 3, Lines 20-37):
determine an importance level of data to be read from the memory (Col. 11, Lines 1-12);
perform, for data with importance level 1, a first level read operation comprising a read operation and a read recovery operation and configured to obtain data with no errors or determine that the read operation is failed when data without errors cannot be obtained (Col. 10, Line 61 - Col. 11, Line 36; Fig. 8);
and perform, for data with importance level 2, a second level read operation comprising a read operation and a read recovery operation and configured to terminate a read recovery operation when a preset termination condition is satisfied (Col. 10, Line 61 - Col. 11, Line 36; Fig. 8).
Allowable Subject Matter
Claims 1-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Although references cited teach parts of the method or the structure of the invention, the combination of all of the parts of the method being executed using the claimed structure was not found. The parts of the method and the structure of the system cannot be obviously combined, and thus the limitations in combination render Claim 1 as allowable, and the dependents, Claims 2-20, follow due to also being a part of that specific combination. In particular, the structure of the system, the prioritization, and the order of operations with respect to termination conditions cannot be found in the art or reasonably combined together. Please see Cai, Basu, and other references cited below for further details.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 23-24 and 27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With regards to Claim 23, Basu teaches using hard error decoding for high priority data and soft error decoding for low priority data. Other systems also teach using either hard or soft decoding and prioritization. In many systems where both hard and soft decoding are performed on the same data, there is no priority scheme. Pream et al. teaches prioritization and hard decoding followed by soft decoding, but teaches multiple iterations of these decoding operations instead of simply terminating once an iteration is complete. While different elements of the method can be found in the art, motivation to combine these elements cannot be found in the art, thus rendering Claim 23 as containing allowable subject matter. Please see the references cited below for further details.
With regards to Claim 24, in Basu, while RBER is tracked as latency information (Paragraph 0025) and the latency information is used to determine if the recovery operations should continue (Paragraph 0043), the termination condition is not explicitly based on a bit error rate being less than or equal to a preset value. This exact type of termination condition cannot be found in a system with the same structure as Claim 24, and there would be no motivation to combine a reference to create this exact condition, thus rendering Claim 24 as containing allowable subject matter.
With regards to Claim 27, while it is known to prioritize the recovery of data based on read frequencies, such as in Lee, or by the type of task, such as in Fu et al. (both cited below), prioritizing the recovery of data based on a frequency of data that is read during a background operation cannot be found within the art, particularly within a similar type of system to the one claimed, thus rendering Claim 27 as containing allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Anholt et al. (U.S. Patent No. 8,429,498 B1): teaches hard decoding followed by soft decoding
Cho et al. (U.S. Publication No. 2020/0373944 A1): teaches hard and soft decoding
Fu et al. (U.S. Publication No. 2017/0168895 A1): teaches prioritizing ECC decoding by the type of task
Ha et al. (U.S. Publication No. 2016/0210190 A1): teaches hard and soft decoding
Ha et al. (U.S. Publication No. 2016/0179616 A1): teaches hard and soft decoding
Halperin et al. (U.S. Publication No. 2020/0234772 A1): teaches analyzing BER and soft and hard decoding
Jang (U.S. Publication No. 2024/0290403 A1): teaches hard and soft decoding with queues
Lee (U.S. Publication No. 2019/0196958 A1): teaches queues to prioritize read reclaim in part by read frequency
Li (U.S. Publication No. 2018/0226990 A1): teaches hard and soft decoding
Losh et al. (U.S. Publication No. 2015/0012794 A1): teaches prioritizing by the type of correction
Pream et al. (U.S. Publication No. 2015/0074488 A1): teaches prioritization, hard decoding followed by soft decoding, and multiple decoders
Ryu et al. (U.S. Publication No. 2021/0334034 A1): teaches prioritizing data recovery
Song (U.S. Publication No. 2025/0125000 A1): teaches prioritizing error correction
Yang (U.S. Publication No. 2024/0403161 A1): teaches prioritizing data that failed hard decoding for soft decoding
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIELLA SHELTON whose telephone number is (571)272-3117. The examiner can normally be reached Monday-Friday 8AM-3PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571) 272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.K.S./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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