Prosecution Insights
Last updated: October 01, 2026
Application No. 19/084,432

SIGNALING OF TIME FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS USING MULTI-DROP BUS

Final Rejection §102§Other
Filed
Mar 19, 2025
Priority
Feb 10, 2020 — provisional 62/972,566 +4 more
Examiner
DALEY, CHRISTOPHER ANTHONY
Art Unit
Tech Center
Assignee
Apple Inc.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
1y 1m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
702 granted / 836 resolved
+24.0% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
11 currently pending
Career history
845
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
58.0%
+18.0% vs TC avg
§102
28.8%
-11.2% vs TC avg
§112
1.4%
-38.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 836 resolved cases

Office Action

§102 §Other
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1 – 20 are pending. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless - (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1- 20 are rejected under 35 U.S.C. 102a1 as being anticipated by O'Shea et al (US20190227962) hereinafter O'Shea. As to claim 1, O'Shea discloses an integrated circuit, comprising: a plurality of communication systems (Fig. 15, with a plurality of communication systems such as modules 1518, 1520, 1522, para. 0095); and a dispatcher circuit (Fig. 15, and dispatcher module 1506) to: receive messages from another integrated circuit (Fig. 15 with data exchange between 1504 and 1518, para. 0095); determine a message from the messages intended for the plurality of communication systems (Fig. 15, where module 1506 manages data flow between it and the plurality of radios, para. 0095); and provide the message to the plurality of communication systems based on an event (Fig. 15, where coexistence messenger 1506 with event manager 1528 determine where message is delivered, and its format of delivery, para. 0096). As to claim 8, O'Shea discloses a method, comprising: receive, by a first integrated circuit, messages from a second integrated circuit (Fig. 15, with a plurality of communication systems such as modules 1518, 1520, 1522, receiving messages from a first integrated circuit, coexistence messenger, 1506, para. 0095); determining a message from the messages intended for a communication system of a plurality of communication systems of the first integrated circuit (Fig. 15, where module 1506 manages data flow between it and the plurality of radios, para. 0095); and providing, by the first integrated circuit, the message to the one of the plurality of communication systems based on an event (Fig. 15, where coexistence messenger 1506 with event manager 1528 determine where message is delivered, and its format of delivery, para. 0096). As to claim 15, O'Shea discloses a system comprising: a first integrated circuit (Fig. 1, and circuit 106); and a second integrated circuit configured to: receive messages from the first integrated circuit (Fig. 15, and circuits 1504, para. 0095); determine a message from the messages intended for one of plurality of communication systems of the second integrated circuit (Fig. 15, with a plurality of communication systems such as modules 1518, 1520, 1522, receiving messages from a first integrated circuit, coexistence messenger, 1506, para. 0095); and provide the message to the one of the plurality of communication systems based on an event (Fig. 15, where coexistence messenger 1506 with event manager 1528 determine where message is delivered, and its format of delivery, para. 0096). As to claims 2, 9, and 16, O'Shea discloses the integrated circuit, wherein the dispatcher circuit is further configured to: generate an interrupt signal based on another message from the messages (Fig. 15 where module 1506 receives message from peripheral such as 1518, para. 0096); and provide the interrupt signal to another one of the plurality of communication systems (Fig. 15 , where module 1506 delivers request to processor 1504, para. 0096) based on an event (Fig. 15, with event manager 1528 determine where message is delivered, and its format of delivery, para. 0096). As to claims 3, 10, and 17, O'Shea discloses the integrated circuit, wherein the interrupt signal is configured to cause the other the plurality of communication systems to perform at least one of: transition to a particular power state (Fig. 4, with power track module 422 that senses the state, para. 0062); or report a status thereof (Fig. 4 where power status is monitored, para. 0062). As to claims 4, 11, and 18, O'Shea discloses the integrated circuit, wherein the dispatcher circuit is further configured to: determine a first time at which each of the messages is received from the other integrated circuit (Fig. 8 with start at 806, and para. 0070); and determine a second time at which the message is provided to the plurality of communication systems (Fig. 8 and the second time, para. 0071). As to claims 5, 12, and 19, O'Shea discloses the integrated circuit, wherein, to determine the first time and the second time, the dispatcher circuit is configured to: determine the first time and the second time based on at least one of: a local clock signal of the integrated circuit (Fig. 8 with clock SCLK 804, para. 0070; or a global clock signal associated with the integrated circuit and the other integrated circuit (common clock between devices, para. 0072). As to claims 6, 13, and 20, O'Shea discloses the integrated circuit, wherein the event comprises at least one of: a determination that the message has a particular priority level (Fig. 9, and para. 0075); or a determination that arbitration for utilizing a bus to provide the message is successful (Fig. 9, and arbitration between communication links). As to claims 7, and 14, O'Shea discloses the integrated circuit, wherein, to determine the message from the messages intended for the plurality of communication systems, the dispatcher circuit is configured to: determine that a rule of a predefined set of rules associated with the plurality of communication systems is satisfied (Fig. 3 with state machine determining the arbitration and other protocols, para. 0058). Response to Arguments Applicants’ arguments filed 9/2/26 have been fully considered but they are not persuasive. The Applicant has argued that the applied prior art O’Shea does not teach a dispatcher circuit configured to determine a message from a message intended for one of a plurality of communication system. In response, the Examiner points to the embodiment of Fig. 15, and dispatcher module 1506: receive messages from another integrated circuit (Fig. 15 and second integrated circuit module such as chipset 1518 via shared bus 1512). Thus, prior art clearly teaches a module coupled between devices that manages the transactions (para. 0095, 0096, and thus rejection is maintained). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER ANTHONY DALEY whose telephone number is (571)272-3625. The examiner can normally be reached 7 - 3:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached at 571 2724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.A.D/Examiner, Art Unit 2184 /HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
Read full office action

Prosecution Timeline

Mar 19, 2025
Application Filed
Jun 01, 2026
Response after Non-Final Action
Jun 02, 2026
Non-Final Rejection mailed — §102, §Other
Aug 11, 2026
Applicant Interview (Telephonic)
Aug 14, 2026
Examiner Interview Summary
Sep 02, 2026
Response Filed
Sep 23, 2026
Final Rejection mailed — §102, §Other (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
94%
With Interview (+10.5%)
2y 7m (~1y 1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 836 resolved cases by this examiner. Grant probability derived from career allowance rate.

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