DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the latch" in page 2 line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 6 recites the limitation "the latch" in page 2 line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation "the latch" in page 2 line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "the latch" in page 2 line 10. There is insufficient antecedent basis for this limitation in the claim.
Claims 9-12 are directly/indirectly depending on claim 8. Therefore, claims 9-12 are rejected for the same reasons as set forth in claim 8 above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the applicant's cited reference US 2019/0259433 (Penney et al hereinafter Penney) .
Regarding claim 1, Penney discloses a clock generation circuit (figs. 2, 24A, 24B, item 82), the clock generation circuit being configured to generate N target clock signals (fig. 24B, items 400, 402, 404, 554), N being a positive even number (N=4), and the clock generation circuit comprising N clock generation sub-circuits (fig. 24A, items 508, 506, 504, 502; fig. 24B, 502, 576, 558 being a sub-circuit, para. [0100]); an ith clock generation sub-circuit (items 502, 506) being configured to: receive an ith register input signal, an inverted clock signal (Clkf), and a delayed clock signal (Wrstart 530 connected to registers 534-558, para. [0099]); perform sampling processing and latching processing on the ith register input signal based on the inverted clock signal, to generate an ith register signal (registers 504, 508, generating 556, 544); and perform first logic processing on the ith register signal and the delayed clock signal (processing of corresponding NAND gates 570-576, flip-flops 534-558, muxes 562-568, in
fig. 24B), to generate an ith target clock signal (554, 402), i being a positive odd number greater than or equal to 1 and less than N, the ith register input signal being an initial register signal when i=1 (WrCmdB in fig. 24A), and the ith register input signal being an (i-1)th register signal when i>1 (register chain in fig. 2 4A); a jth clock generation sub-circuit (fig. 24A, 504, 508) being configured to: receive a (j-1)th register signal, a preset clock signal, and the delayed clock signal (fig. 24B, 550, 538); perform sampling processing and latching processing on the (j-1)th register signal based on the preset clock signal, to generate a jth register signal (registers 504, 508, generating 550,
538); and perform second logic processing on the jth register signal and the delayed clock signal, to generate a jth target clock signal, j being a positive even number greater than 1 and less than or equal to N (similar as above); and the preset clock signal and the inverted clock signal being a pair of inverted signals, and the delayed clock signal being a delayed signal of the preset clock signal (see fig. 24A; paragraphs [0099],
regarding Wrstart, and paragraph [0108], regarding the Clk, ClkF notation).
Regarding claim 4, Penney also shows the clock generation circuit further comprising a first AND gate; and a first input terminal of the first AND gate being configured to receive a 1st target clock signal, a second input terminal of the first AND gate being configured to receive an Nth register signal, and an output terminal of the first AND gate being configured to output the initial register signal (fig. 24B, 570-576).
Regarding claim 5, as best understood 112 2nd rejection above, Penney also shows wherein the jth latch is further configured to: receive a reset signal, and reset, based on the reset signal, the j th register signal output by the latch (fig. 24A, RstfF).
Regarding claim 13, Penney also teaches a memory, the memory comprising the clock generation circuit according to claim 1 (fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Penney and in view of US20040153626 (Saito).
Regarding claims 2 and 3, Penney does teach the second logic processing is NAND logic processing (see fig. 24B).
Penney does not explicitly disclose wherein the first logic processing is OR logic processing.
However, the OR logic processing is notorious old and well known.
For instance, in the related field of the invention, Saito teaches a semiconductor device includes a state code register that stores a state code representing a present internal state. A state transition logic unit is configured to determine a state code for a next internal state to be transited in accordance with a predetermined logic, based on a state code provided from the state code register and an input command instructing transition to a required state, and to set the determined state code into the state code register with synchronizing an internal clock. An expected value register is configured to hold an internal state to be detected, as an expected value code and a comparing unit compares the state code set in the state code register by the state transition logic unit to the expected value code in the expected value register and supplying an equal state signal when they coincide and the internal interrupt generating circuit 78 includes an AND gate 90 and an OR gate 91 (abstract and fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to use the well-known OR logic processing by Saito in Penney for a particular application.
Claim(s) 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Penney.
Regarding claims 6 and 7, as best understood 112 2nd rejection above, Penney does teach first and second reset signals which enable register outputs in different states, to guarantee glitch free output and a deterministic initial clock output state (see Rstf and Set in figs. 24A and 24B).
Penney does not explicitly disclose an alternative set/reset control of the registers.
However, Penney does not limit to a specific technique (para. [0113], [0114]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify Penney for an alternative set/reset control of the registers in order to achieve a desired outcome.
Allowable Subject Matter
Claims 8-12 are objected to as being dependent upon a rejected base claim and overcome 112 2nd rejections above but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior art of record fails to teach the limitation of claim 8 “ the clock generation circuit further comprising a signal generation circuit; and the signal generation circuit being configured to: receive an initial clock signal, and perform first delay processing on the initial clock signal, to generate the preset clock signal; perform second delay processing and inversion processing on the initial clock signal, to generate the inverted clock signal; and perform third delay processing on the initial clock signal, to generate the delayed clock signal, duration of the first delay processing and duration of the second delay processing being the same and being both less than duration of the third delay processing, and a difference between the duration of the third delay processing and each of the duration of the first delay processing and the duration of the second delay processing being delay duration of the latch.“. Therefore, the prior art teachings are neither anticipate nor render obvious the allowable subject matter in combination with the other claimed limitations.
Conclusion
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/TUAN D NGUYEN/Primary Examiner, Art Unit 2824
