DETAILED ACTION
This is in response to the application filed on March 20, 2025 in which claims 1 – 20 are presented for examination.
Status of Claims
Claims 1 – 20 are pending, of which claims 1, 9, 11, 14, 17, and 19 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 7, 9 – 15, 17 – 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 18 of U.S. Patent No. 12,282,775. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are broader than the claims of U.S. Patent 12,282,775.
12,282,775
19/084811
1. A network device, comprising: one or more ports, to exchange packets between the network device and a network;
match-action circuitry, to match at least some of the packets to one or more rules so as to set respective actions to be performed, wherein at least one of the actions comprises a programmable action; and
an instruction processor, to perform the programmable action by running user-programmable software code,
wherein the instruction processor comprises architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and
wherein the match-action circuitry is to write into the architectural registers information for performing the programmable action, the information comprising at least a value indicative of a start address of the user-programmable software code performing the programmable action.
1. A device, comprising: one or
more ports, to exchange packets between the device and a network;
match-action circuitry, to match at least some of the packets to one or more rules so as to set respective actions to be performed, wherein at least one of the actions comprises a programmable action; and
an instruction processor, to perform the programmable action by running user-programmable software code,
wherein the match-action circuitry is to provide the instruction processor with information for performing the programmable action, the information comprising at least a value indicative of a start address of the user-programmable software code performing the programmable action.
2. The network device according to claim 1, wherein the match-action circuitry is to instruct the instruction processor to perform the programmable action using the information written into the architectural registers.
3. The network device according to claim 1, wherein the match-action circuitry is to perform one or more of the actions that are non-programmable.
4. The network device according to claim 1, wherein the match-action circuitry is to distinguish between programmable actions and non-programmable actions, and to trigger the instruction processor to perform the programmable actions.
5. The network device according to claim 1, wherein the instruction processor comprises one or more Reduced Instruction Set Computer (RISC) cores.
6. The network device according to claim 1, wherein the instruction processor comprises an internal memory, and is to run the user-programmable code entirely from the internal memory.
7. The network device according to claim 1, wherein the instruction processor is to run the user-programmable code from an external memory, using an instruction cache that is to cache instructions of the user-programmable code.
2. The device according to claim 1, wherein the match-action circuitry is to instruct the instruction processor to perform the programmable action using the provided information.
3. The device according to claim 1, wherein the match-action circuitry is to perform one or more of the actions that are non-programmable.
4. The device according to claim 1, wherein the match-action circuitry is to distinguish between programmable actions and non-programmable actions, and to trigger the instruction processor to perform the programmable actions.
5. The device according to claim 1, wherein the instruction processor comprises one or more Reduced Instruction Set Computer (RISC) cores.
6. The device according to claim 1, wherein the instruction processor comprises an internal memory, and is to run the user-programmable code entirely from the internal memory.
7. The device according to claim 1, wherein the instruction processor is to run the user-programmable code from an external memory, using an instruction cache that is to cache instructions of the user-programmable code.
15. A network device, comprising: one or more ports, to exchange packets between the network device and a network;
match-action circuitry, to match at least some of the packets to one or more rules so as to set respective actions to be performed, wherein at least one of the actions comprises a stateful programmable action that depends on state information stored in a memory; and an instruction processor, to perform the stateful programmable action by running user-programmable software code,
wherein the instruction processor comprises architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and wherein the match-action circuitry is to retrieve the state information from the memory and to write the retrieved state information into the architectural registers, for performing the stateful programmable action.
9. A device, comprising: one or
more ports, to exchange packets between the device and a network;
match-action circuitry, to match at least some of the packets to one or more rules so as to set respective actions to be performed, wherein at least one of the actions comprises a stateful programmable action that depends on state information stored in a memory; and an instruction processor, to perform the stateful programmable action by running user-programmable software code,
wherein the match-action circuitry is to retrieve the state information from the memory and to provide the retrieved state information to the instruction processor, for performing the stateful programmable action.
16. The network device according to claim 15, wherein, following the completion of the stateful programmable action, the match-action circuitry is to read updated state information from the architectural registers and to save the updated state information in the memory.
10. The device according to claim 9, wherein, following
completion of the stateful programmable action, the match-action circuitry is to receive updated state information from the instruction processor and to save
the updated state information in the memory.
8. A network device, comprising: one or more ports, to exchange packets between the network device and a network;
match-action circuitry, to match at least some of the packets to one or more rules so as to set respective actions to be performed, wherein at least one of the actions comprises a programmable action; and an instruction processor, to perform the programmable action by running user-programmable software code,
wherein the instruction processor comprises architectural registers, one or more of the architectural registers being accessible by the match-action circuitry,
wherein the match-action circuitry is to write into the architectural registers information for performing the programmable action, wherein the instruction processor comprises an execution pipeline to run the user-programmable software code, and wherein the match-action circuitry is to trigger the execution pipeline after writing state information to the architectural registers.
11. A device, comprising: one or
more ports, to exchange packets between the device and a network;
match-action circuitry, to match at least some of the packets to one or more rules so as to set respective actions to be performed, wherein at least one of the actions comprises a programmable action; and an instruction processor, to perform the programmable action by running user-programmable software code,
wherein the match-action circuitry is to provide the instruction processor with information for performing the programmable action, and wherein the instruction processor comprises an execution pipeline to run the user-programmable software code, and wherein the match-action circuitry is to trigger the execution pipeline after providing the information.
9. The network device according to claim 8, wherein the execution pipeline supports Arithmetic Logic Unit (ALU) operations and flow-control operations, but does not support memory load and store operations.
10. The network device according to claim 8, wherein the execution pipeline supports memory load and store operations.
12. The device according to claim 11, wherein the execution pipeline
supports Arithmetic Logic Unit (ALU) operations and flow-control operations, but does not support memory load and store operations.
13. The device according to claim 11, wherein the execution pipeline
supports memory load and store operations.
11. A method, comprising: exchanging packets between a network device and a network;
matching at least some of the packets to one or more rules using match-action circuitry in the network device, so as to set respective actions to be performed, wherein at least one of the actions comprises a programmable action; and performing the programmable action by running user-programmable software code on an instruction processor in the network device, including writing, by the match-action circuitry, information for performing the programmable action into one or more architectural registers of the instruction processor that are accessible by the match-action circuitry, the information comprising at least a value indicative of a start address of the user-programmable software code performing the programmable action.
14. A method, comprising: exchanging packets between a device and a network;
matching at least some of the packets to one or more rules using match-action circuitry in the device, so as to
set respective actions to be performed, wherein at least one of the actions comprises a programmable action; and performing the programmable action by running user-programmable software code on an instruction processor in the device, including providing to the instruction processor, by the match-action circuitry, information for performing the programmable action,
the
information comprising at least a value indicative of a start address of the user-programmable software code performing the programmable action.
12. The method according to claim 11, and comprising, using the match-action circuitry, distinguishing between programmable actions and non-programmable actions, and triggering the instruction processor to perform the programmable actions.
15. The method according to claim 14, and comprising, using the match-action circuitry, distinguishing between programmable actions and non-programmable actions, and triggering the instruction processor to perform the programmable actions.
17. A method, comprising: exchanging packets between a network device and a network;
matching at least some of the packets to one or more rules using match-action circuitry in the network device, so as to set respective actions to be performed, wherein at least one of the actions comprises a stateful programmable action that depends on state information stored in a memory; using the match-action circuitry, retrieving the state information from the memory and writing the retrieved state information into one or more architectural registers of an instruction processor in the network device, for performing the programmable action; and performing the stateful programmable action by running the user-programmable software code on the instruction processor.
17. A method, comprising: exchanging packets between a device and a network;
matching at least some of the packets to one or more rules using match-action circuitry in the device, so as to set respective actions to be performed, wherein at least one of the actions comprises a stateful programmable action that depends on state information stored in a memory; using the match-action circuitry, retrieving the state information from the memory and providing the retrieved state information to an instruction processor in the device,
for
performing the programmable action; and performing the
stateful programmable action by running the user-programmable software code on the instruction processor.
18. The method according to claim 17, and comprising, following completion of the stateful action, reading updated state information from the architectural registers by the match-action circuitry, and saving the updated state information in the memory.
18. The method according to claim 17, and comprising, following completion of the stateful action, receiving updated state information from the instruction processor by the match-action circuitry, and saving the updated state information in the memory.
13. A method, comprising: exchanging packets between a network device and a network;
matching at least some of the packets to one or more rules using match-action circuitry in the network device, so as to set respective actions to be performed, wherein at least one of the actions comprises a programmable action; and performing the programmable action by running user-programmable software code on an instruction processor in the network device, including writing, by the match-action circuitry, information for performing the programmable action into one or more architectural registers of the instruction processor that are accessible by the match-action circuitry, wherein performing the programmable action comprises, using the match-action circuitry, triggering an execution pipeline of the instruction processor after writing state information to the architectural registers.
19. A method, comprising: exchanging packets between a device and a network;
matching at least some of the packets to one or more rules using match-action circuitry in the device, so as to
set respective actions to be performed, wherein at least one of the actions comprises a programmable action; and performing the programmable action by running user-programmable software code on an instruction processor in the device, including providing to the instruction processor, by the match-action circuitry, information for performing the programmable action,
wherein
performing the programmable action comprises, using the match-action circuitry, triggering an execution pipeline of the instruction processor after providing the information.
14. The method according to claim 13, wherein the execution pipeline supports Arithmetic Logic Unit (ALU) operations and flow-control operations, but does not support memory load and store operations.
20. The method according to claim 19, wherein the execution pipeline supports Arithmetic Logic Unit (ALU) operations and flow-control operations, but does not support memory load and store operations.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 5, 7, 11, 14, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Urman et al., U.S. Patent Application 2021/0176345 (hereinafter referred to as Urman) in view of Subrahmanya et al., U.S. Patent Application 2022/0045940 (hereinafter referred to as Subrahmanya).
Referring to claim 1, Urman discloses “A device” (Fig. 1 network device 10), “comprising: one or more ports, to exchange packets between the device and a network” (Fig. 1 network interfaces 12 and [0044] The network device 10 includes at least one network interface 12 configured to operate as at least ingress port and at least one egress port for receiving packets from, and sending packets to, a packet data network 14); “match-action circuitry, to match at least some of the packets to one or more rules so as to set respective actions to be performed” ([0048] The packet processing engine 20 uses the match and action tables 28 to determine how each packet should be processed according to the parsed information generated by the hardware parsers 18), “wherein at least one of the actions comprises a programmable action” ([0049] if a MAC address in the header section is matched to a given MAC address then the packet is to be reparsed by the hardware parsers 18 after the parser configuration registers 24 are loaded with parsing configuration data set A. In this example, the packet processing engine 20 instructs the controller 22 to load parsing configuration data set A from the cache memory 26 and send the header section, or a link to the header section in the buffer 16, to the hardware parsers 18 so that the header section can be reparsed according to parsing configuration data set A); “and an instruction processor, to perform the programmable action by running user-programmable software code” ([0050] at least some of the functions of the packet processing engine 20 may be carried out by a programmable processor under the control of suitable software. Also note that Urman teaches at [0050] that some or all of the functions of the packet processing engine 20 may be combined in a single physical component or, alternatively, implemented using multiple physical components. These physical components may comprise hard-wired or programmable devices, or a combination of the two. Thus, one of these components is considered equivalent to ‘an instruction processor’), “wherein the match-action circuitry is to provide the instruction processor with information for performing the programmable action” ([0076] The packet processing engine 20 is configured to cause loading (block 210) of the selected parsing configuration data set from the cache memory 26 into the parser configuration registers 24. [0076] The packet processing engine 20 is configured to cause loading (block 210) of the selected parsing configuration data set from the cache memory 26 into the parser configuration registers 24).
Urman does not appear to explicitly disclose “the information comprising at least a value indicative of a start address of the user-programmable software code performing the programmable action.”
However, Subrahmanya discloses another network device using match-action (Abstract) wherein “the information comprising at least a value indicative of a start address of the user-programmable software code performing the programmable action” ([0087] loading programs upon receiving the start address of the program).
Urman and Subrahmanya are analogous art because they are from the same field of endeavor, which is match-action circuitry and programmable processors.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Urman and Subrahmanya before him or her, to modify the teachings of Urman to include the teachings of Subrahmanya so that the match-action circuitry provides a start address of code to the instruction processor.
The motivation for doing so would have been to provide flexibility to allow for executing different programs associated with different types of data using the same processing unit (as described by Subrahmanya at [0087]).
Therefore, it would have been obvious to combine Subrahmanya with Urman to obtain the invention as specified in the instant claim.
As per claim 2, Urman discloses “the match-action circuitry is to instruct the instruction processor to perform the programmable action using the provided information” ([0076] The packet processing engine 20 is configured to cause loading (block 210) of the selected parsing configuration data set from the cache memory 26 into the parser configuration registers 24).
As per claim 3, Urman discloses “the match-action circuitry is to perform one or more of the actions that are non-programmable” ([0049] “if the parsed information includes data D, then the header section is amended. By way of yet another example, if the parsed information includes data E, then the packet is sent back to the packet data network 14 on port F”, [0078] processing the packet using match action tables. Also, note that Urman teaches at [0050] that some or all of the functions of the packet processing engine 20 may be combined in a single physical component or, alternatively, implemented using multiple physical components. These physical components may comprise hard-wired or programmable devices, or a combination of the two.).
As per claim 4, Urman discloses “the match-action circuitry is to distinguish between programmable actions and non-programmable actions, and to trigger the instruction processor to perform the programmable actions” ([0049] “if a MAC address in the header section is matched to a given MAC address, then the packet is to be reparsed by the hardware parsers 18 after the parser configuration registers 24 are loaded with parsing configuration data set A. In this example, the packet processing engine 20 instructs the controller 22 to load parsing configuration data set A from the cache memory 26” and [0049] “if the parsed information includes data D, then the header section is amended. By way of yet another example, if the parsed information includes data E, then the packet is sent back to the packet data network 14 on port F.” [0076] The packet processing engine 20 is configured to cause loading (block 210) of the selected parsing configuration data set from the cache memory 26 into the parser configuration registers 24).
As per claim 5, Urman does not appear to explicitly disclose “the instruction processor comprises one or more Reduced Instruction Set Computer (RISC) cores.”
However, Subrahmanya discloses “the instruction processor comprises one or more Reduced Instruction Set Computer (RISC) cores” ([0072], [0080] RISC).
As per claim 7, Urman discloses “the instruction processor is to run the user-programmable code from an external memory, using an instruction cache that is to cache instructions of the user-programmable code” (Fig. 1 cache memory 26 holding parsing configuration data sets 32 and [0076] The packet processing engine 20 is configured to cause loading (block 210) of the selected parsing configuration data set from the cache memory 26 into the parser configuration registers 24).
Referring to claim 11, Urman discloses “A device” (Fig. 1 network device 10), “comprising: one or more ports, to exchange packets between the device and a network” (Fig. 1 network interfaces 12 and [0044] The network device 10 includes at least one network interface 12 configured to operate as at least ingress port and at least one egress port for receiving packets from, and sending packets to, a packet data network 14); “match-action circuitry, to match at least some of the packets to one or more rules so as to set respective actions to be performed” ([0048] The packet processing engine 20 uses the match and action tables 28 to determine how each packet should be processed according to the parsed information generated by the hardware parsers 18), “wherein at least one of the actions comprises a programmable action” ([0049] if a MAC address in the header section is matched to a given MAC address then the packet is to be reparsed by the hardware parsers 18 after the parser configuration registers 24 are loaded with parsing configuration data set A. In this example, the packet processing engine 20 instructs the controller 22 to load parsing configuration data set A from the cache memory 26 and send the header section, or a link to the header section in the buffer 16, to the hardware parsers 18 so that the header section can be reparsed according to parsing configuration data set A); “and an instruction processor, to perform the programmable action by running user-programmable software code” ([0050] at least some of the functions of the packet processing engine 20 may be carried out by a programmable processor under the control of suitable software. Also note that Urman teaches at [0050] that some or all of the functions of the packet processing engine 20 may be combined in a single physical component or, alternatively, implemented using multiple physical components. These physical components may comprise hard-wired or programmable devices, or a combination of the two. Thus, one of these components is considered equivalent to ‘an instruction processor’), “wherein the match-action circuitry is to provide the instruction processor with information for performing the programmable action” ([0076] The packet processing engine 20 is configured to cause loading (block 210) of the selected parsing configuration data set from the cache memory 26 into the parser configuration registers 24. [0076] The packet processing engine 20 is configured to cause loading (block 210) of the selected parsing configuration data set from the cache memory 26 into the parser configuration registers 24).
Urman does not appear to explicitly disclose “wherein the instruction processor comprises an execution pipeline to run the user-programmable software code, and wherein the match-action circuitry is to trigger the execution pipeline after providing the information.”
However, Subrahmanya discloses another network device using match-action (Abstract) wherein “the instruction processor comprises an execution pipeline to run the user-programmable software code, and wherein the match-action circuitry is to trigger the execution pipeline after providing the information” (Abstract – pipeline. [0127] match-action pipeline implemented via a packet processing circuit to process network traffic flows, [0141] configuring a match-action pipeline to process new network traffic flows, and [0142] selecting a flow processor worker).
Urman and Subrahmanya are analogous art because they are from the same field of endeavor, which is match-action circuitry and programmable processors.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Urman and Subrahmanya before him or her, to modify the teachings of Urman to include the teachings of Subrahmanya so that the instruction processor comprises an execution pipeline to run the user-programmable software code and the match-action circuitry is to trigger the execution pipeline after providing the information.
The motivation for doing so would have been to provide flexibility to allow for executing different programs associated with different types of data using the same processing unit (as described by Subrahmanya at [0087]).
Therefore, it would have been obvious to combine Subrahmanya with Urman to obtain the invention as specified in the instant claim.
Referring to claim 14, claim 1 recites the corresponding limitations as that of claim 14. Therefore, the rejection of claim 1 applies to claim 14.
Note, claim 15 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 15.
Referring to claim 19, claim 11 recites the corresponding limitations as that of claim 19. Therefore, the rejection of claim 11 applies to claim 19.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Urman in view of Subrahmanya, as applied to claims above, further in view of Bosshart et al., ‘Forwarding Metamorphosis: Fast Programmable Match-Action Processing in Hardware for SDN’ (hereinafter referred to as Bosshart).
As per claim 6, neither Urman nor Subrahmanya appears to explicitly disclose “the instruction processor comprises an internal memory, and is to run the user-programmable code entirely from the internal memory.”
However, Bosshart discloses “the instruction processor comprises an internal memory, and is to run the user-programmable code entirely from the internal memory” (Abstract and Figure 4 programmable parser. Section 5.4 the RMT (reconfigurable match tables) model and section 2.2 SRAM to store actions. Section 5.2.1 also details the memories and why they are chosen).
Urman, Subrahmanya, and Bosshart are analogous art because they are from the same field of endeavor, which is programmable processors.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Urman, Subrahmanya, and Bosshart before him or her, to modify the teachings of Urman and Subrahmanya to include the teachings of Bosshart so that the instruction processor is to run the user-programmable code entirely from internal memory.
The motivation for doing so would have been to utilize local memories that provide cheap matching capabilities (as stated by Bosshart in section 2.2).
Therefore, it would have been obvious to combine Bosshart with Urman and Subrahmanya to obtain the invention as specified in the instant claim.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Urman in view of Subrahmanya, as applied to claims above, further in view of Grochowski et al., U.S. Patent Application 2016/0216971 (hereinafter referred to as Grochowski).
As per claim 8, neither Urman nor Subrahmanya appears to explicitly disclose “an Application Programming Interface (API) for loading the user-programmable software code.”
However, Grochowski discloses “an Application Programming Interface (API) for loading the user-programmable software code” (Abstract programming instructions with pointers, [0091] API).
Urman, Subrahmanya, and Grochowski are analogous art because they are from the same field of endeavor, which is programmable processors.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Urman, Subrahmanya, and Grochowski before him or her, to modify the teachings of Urman and Subrahmanya to include the teachings of Grochowski so that an API is used to load the software code.
The motivation for doing so would have been to provide a means for loading software while hiding memory management and security permissions from the developer, making the process easier for the developer.
Therefore, it would have been obvious to combine Grochowski with Urman and Subrahmanya to obtain the invention as specified in the instant claim.
Note, claim 16 recites the corresponding limitations of claim 8. Therefore, the rejection of claim 8 applies to claim 16.
Claims 9, 10, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Urman in view of Chandrasekaran et al., U.S. Patent Application 2023/0069844 (hereinafter referred to as Chandrasekaran).
As per claim 9, Urman discloses “A device” (Fig. 1 network device 10), “comprising: one or more ports, to exchange packets between the device and a network” (Fig. 1 network interfaces 12 and [0044] The network device 10 includes at least one network interface 12 configured to operate as at least ingress port and at least one egress port for receiving packets from, and sending packets to, a packet data network 14); “match-action circuitry, to match at least some of the packets to one or more rules so as to set respective actions to be performed” ([0048] The packet processing engine 20 uses the match and action tables 28 to determine how each packet should be processed according to the parsed information generated by the hardware parsers 18), “wherein at least one of the actions comprises a” “programmable action” ([0049] if a MAC address in the header section is matched to a given MAC address then the packet is to be reparsed by the hardware parsers 18 after the parser configuration registers 24 are loaded with parsing configuration data set A. In this example, the packet processing engine 20 instructs the controller 22 to load parsing configuration data set A from the cache memory 26 and send the header section, or a link to the header section in the buffer 16, to the hardware parsers 18 so that the header section can be reparsed according to parsing configuration data set A); “and an instruction processor, to perform the" “programmable action by running user-programmable software code” ([0050] at least some of the functions of the packet processing engine 20 may be carried out by a programmable processor under the control of suitable software. Also note that Urman teaches at [0050] that some or all of the functions of the packet processing engine 20 may be combined in a single physical component or, alternatively, implemented using multiple physical components. These physical components may comprise hard-wired or programmable devices, or a combination of the two. Thus, one of these components is considered equivalent to ‘an instruction processor’), “wherein the match-action circuitry is” “to provide the” information to the instruction processor, for performing the” “programmable action” ([0076] The packet processing engine 20 is configured to cause loading (block 210) of the selected parsing configuration data set from the cache memory 26 into the parser configuration registers 24. [0076] The packet processing engine 20 is configured to cause loading (block 210) of the selected parsing configuration data set from the cache memory 26 into the parser configuration registers 24).
Urman does not appear to explicitly disclose “wherein at least one of the actions comprises a stateful programmable action that depends on state information stored in a memory; and an instruction processor, to perform the stateful programmable action by running user-programmable software code, wherein the match-action circuitry is to retrieve the state information from the memory and to provide the retrieved state information to the instruction processor, for performing the stateful programmable action.”
However, Chandrasekaran discloses “wherein at least one of the actions comprises a stateful programmable action that depends on state information stored in a memory” and “retriev[ing] the state information from the memory” ([0006] data structure in a state, updated to a second state, pipeline including match action unit, produce state transition data and send the state sync packet).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Chandrasekaran with Urman so that at least one of the actions comprises a stateful programmable action that depends on state information stored in a memory and the match-action circuitry retrieves and provides the state information.
Urman and Chandrasekaran are analogous art because they are from the same field of endeavor, which is match-action circuitry and network devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Urman and Chandrasekaran before him or her, to modify the teachings of Urman to include the teachings of Chandrasekaran so that at least one of the actions comprises a stateful programmable action that depends on state information stored in a memory and the match-action circuitry retrieves and provides the state information.
The motivation for doing so would have been to provide a means for maintaining synchronization of data structures on network devices (as described by Chandrasekaran at [0006] – [0008]).
Therefore, it would have been obvious to combine Chandrasekaran with Urman to obtain the invention as specified in the instant claim.
As per claim 10, Urman discloses “the match-action circuitry” ([0048] The packet processing engine 20 uses the match and action tables 28) and “the instruction processor” ([0050] at least some of the functions of the packet processing engine 20 may be carried out by a programmable processor under the control of suitable software. Also note that Urman teaches at [0050] that some or all of the functions of the packet processing engine 20 may be combined in a single physical component or, alternatively, implemented using multiple physical components. These physical components may comprise hard-wired or programmable devices, or a combination of the two. Thus, one of these components is considered equivalent to ‘an instruction processor’).
Chandrasekaran discloses “following completion of the stateful programmable action,” “receive updated state information” “and to save the updated state information in the memory” ([0006] – [0008] updating local data structures of peer devices).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Chandrasekaran with Urman so that the match-action circuitry is to receive updated state information from the instruction processor.
Urman and Chandrasekaran are analogous art because they are from the same field of endeavor, which is match-action circuitry and network devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Urman and Chandrasekaran before him or her, to modify the teachings of Urman to include the teachings of Chandrasekaran so that at least one of the actions comprises a stateful programmable action that depends on state information stored in a memory and the match-action circuitry retrieves and provides the state information.
The motivation for doing so would have been to provide a means for maintaining synchronization of data structures on network devices (as described by Chandrasekaran at [0006] – [0008]).
Therefore, it would have been obvious to combine Chandrasekaran with Urman to obtain the invention as specified in the instant claim.
Referring to claim 17, claim 9 recites the corresponding limitations as that of claim 17. Therefore, the rejection of claim 9 applies to claim 17.
Note, claim 18 recites the corresponding limitations of claim 10. Therefore, the rejection of claim 10 applies to claim 18.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Urman in view of Subrahmanya, as applied to claims above, further in view of Ghiya, U.S. Patent Application 2018/0329711 (hereinafter referred to as Ghiya).
As per claim 13, neither Urman nor Subrahmanya discloses “the execution pipeline supports memory load and store operations.”
However, memory load and store operations are commonly supported in the art. For example, Ghiya discloses another programmable processor system ([0067]) that supports load and store operations ([0027] execution unit may include a load (LD) unit, a store (ST) unit).
Urman, Subrahmanya, and Ghiya are analogous art because they are from the same field of endeavor, which is programmable processors.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Urman, Subrahmanya, and Ghiya before him or her, to modify the teachings of Urman and Subrahmanya to include the teachings of Ghiya so that the pipeline supports memory load and store operations.
The motivation for doing so would have been to provide for a simpler means for accessing memory. The load and store operations are known to provide a standard mechanism for accessing memory instead of allowing multiple different instructions to access memory. This standard mechanism allows for increased performance/speed.
Therefore, it would have been obvious to combine Ghiya with Urman and Subrahmanya to obtain the invention as specified in the instant claim.
Allowable Subject Matter
Claims 12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Also note that claims 12 and 20 are rejected above for double patenting issues.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent 11258885 is the granted patent to Urman.
U.S. Patent Application 2024/0146703 teaches a match-action pipeline with criteria stored in registers.
U.S. Patent Application 2017/0064047 teaches sets of match and action entries to configure a hardware switch.
U.S. Patent Applications 20220045945, 20220417142, 20230064845, 20230068914, 20240223353 and Patents 11374859, 11456952, 11818039, 11876696, 12021963, 12368659, 12381709 are also to Pensando (like Subrahmanya and Chandrasekaran) with similar teachings.
Machine Translation of Korean Patent Application KR 20100063024 A teaches a start address specified in an architectural register.
‘Re-Configurable Match-Action Tables (RMT) - Lecture 16, Computer Networks (198:552)’ Fall 2019 from Rutgers University teaches reconfigurable match-action tables and a pipeline structure.
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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