Prosecution Insights
Last updated: October 25, 2026
Application No. 19/084,852

MULTILAYER CERAMIC CAPACITOR AND CIRCUIT BOARD

Non-Final OA §103§112
Filed
Mar 20, 2025
Priority
Mar 27, 2024 — JP 2024-050663
Examiner
MILAKOVICH, NATHAN J
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiyo Yuden Co., Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
560 granted / 718 resolved
+10.0% vs TC avg
Strong +19% interview lift
Without
With
+19.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
17 currently pending
Career history
735
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
44.5%
+4.5% vs TC avg
§102
25.7%
-14.3% vs TC avg
§112
22.0%
-18.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 718 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The drawings were received on March 20, 2025. These drawings are acceptable. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Objections Claims 1-8 are objected to because of the following informalities: Claim 6 line 3-4: “extends outward with relative to” is not idiomatic English (“extends outward relative to” is suggested). The following claim limitations lack antecedent bases (“a” or “an” is suggested): Claim 1: Line 6: “the stacking direction”; Line 8: “the surface of the protective portion”; Line 8: “the other end”; Line 10: “the surface of the element body”. Claim 2: Line 2: “D1 is the dimension perpendicular”; Line 3: “D2 is the minimum dimension”; Line 4-5: “the opposite side of the protective portion”; Line 6: “the dimension in the direction perpendicular”. Claim 3 line 2: “D3 is the dimension”. Claim 5 line 2: “the end portion”. The remaining claims are objected to by reason of their dependency. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 recites, “the dimension in the stacking direction”, but no element is set forth in claim 7 or independent claim 1 of having “a dimension”. It is ambiguous what element in claim 7 is being limited or establishes “a dimension”. This ambiguity renders claim 7 indefinite, and accordingly, claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Page 5-6 paragraph 16 appears to indicate “the dimension” is the thickness of the multilayer ceramic capacitor. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1 and 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication 2020/0135400 to Sakurai et al. (hereinafter Sakurai) in view of US Publication 2018/0277305 to Kawakami et al. (hereinafter Kawakami). Claim 1 Sakurai (FIG. 1A) discloses a multilayer ceramic capacitor, comprising: a cuboid element body (4) having a stack (13) formed with alternating ceramic layers (10, paragraph 47) and internal electrodes (12, paragraph 53) made primarily of metal, a protective portion (11) covering a surface of the stack (13), and a plurality of via conductors (52) arranged so as to pass through the ceramic layers (10) in the stacking direction of the stack (13), electrically connected to the internal electrodes (12), and having one end reaching the surface of the protective portion (11) while the other end is positioned in the protective portion (11), and a plurality of terminal electrodes (6, 8) arranged on the surface (4c) of the element body (4) and electrically connected to the end of each via conductor (52) reaching the surface of the protective portion (11), as recited in claim 1. Sakurai does not expressly disclose wherein the ends of the via conductors positioned in the protective portion form a flange that extends outwardly relative to the axis of the via conductor, as recited in claim 1. Kawakami (FIG. 1) teaches a via conductor (6, paragraph 30) arranged so as to pass through ceramic layers (3b-3d, paragraph 32) in a stacking direction of a stack (3b-3d), electrically connected to internal electrodes (4b,d, paragraph 30), and having one end reaching a surface of a protective portion (3a,e, paragraph 32) while an other end is positioned in the protective portion (3a,e), wherein the end of the via conductor (6) positioned in the protective portion (3a,e) form a flange (6b, paragraph 34) that extends outwardly relative to an axis of the via conductor (6, paragraph 34-35). It would have been obvious to one of Kawakami skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kawakami with Sakurai to incorporate via flanges as taught by Kawakami in the structure taught by Sakura and thereby have the ends of the via conductors positioned in the protective portion of Sakurai (e.g., FIG. 1A: 52) form a flange that extends outwardly relative to the axis of the via conductor as taught by Kawakami, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for reducing the occurrence of breaks in the inner electrodes, cracks in the ceramic layers, and gaps between the via-electrode and the ceramic layers, and also prevents the via-electrode from detaching from or falling out of the multilayer electronic component, even with the difference in the contraction coefficient between the via-electrode and the ceramic element of the ceramic layers during the firing process (Kawakami paragraph 10). Claim 4 Sakurai with Kawakami teaches the multilayer ceramic capacitor according to claim 1, wherein dimension A1 of the via conductors (Sakurai 52 in view of Kawakami 6b) in the stacking direction of the flange is 0.1 μm or more and 10 μm or less (Kawakami paragraph 59). Claim 5 Sakurai with Kawakami teaches the multilayer ceramic capacitor according to claim 1, wherein the via conductors (Sakurai 52 in view of Kawakami 6b) have a cavity opening in the end portion inside the protective portion (Sakurai 50; note FIG. 1A: the cavity opening 50 is “in the end portion” of via 52). Claim 6 Sakurai with Kawakami teaches the multilayer ceramic capacitor according to claim 1, wherein the via conductors (Sakurai 52 in view of Kawakami 6b) have an end portion reaching the surface of the protective portion (Kawakami 3a,e) that protrudes in the stacking direction beyond the surface of the protective portion (3a,e) and forms a flange (8) that extends outward with relative to the axis of the via conductor (6; see Kawakami FIG. 1, 2A-G, paragraph 43: inkjet printing of via and surface electrodes with same material). Claim 7 Sakurai with Kawakami teaches the multilayer ceramic capacitor according to claim 1, wherein the dimension in the stacking direction is less than 100 μm (Sakruai paragraph 31, FIG. 9). Claim 8 Sakurai with Kawakami teaches a circuit board carrying the multilayer ceramic capacitor according to claims 1 (Sakurai paragraph 2). Allowable Subject Matter Claims 2-3 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and pending resolution of the objections set forth above. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Publication 2021/0005386 (see, e.g., FIG. 3); and US Publication 2025/0149247 (see, e.g., 2). See also similar applications US Publication 2025/0292965; and US Publication 2026/0188585 (but note assignee, inventorship, and effective filing dates). Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN MILAKOVICH whose telephone number is (571)270-3087. The examiner can normally be reached Monday - Friday 9:00 AM - 5:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATHAN MILAKOVICH/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Mar 20, 2025
Application Filed
Sep 30, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 1m to grant Granted Oct 20, 2026
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Patent 12764867
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Patent 12763256
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
97%
With Interview (+19.0%)
2y 5m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 718 resolved cases by this examiner. Grant probability derived from career allowance rate.

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