DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/20/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsidon et al US Patent No. 12,487,759.
Regarding claim 1, Tsidon teaches a method for real-time Direct Memory Access (DMA) and Memory-Mapped I/O (MMIO) threat detection of an embedded system, comprising:
identifying a protection target in an embedded system and inserting a security module for monitoring the identified protection target (see figure 1, hardware monitor 116 for monitoring memory 106, see col 3 ln 50 - col 4 ln 14, utilize one or more hardware monitor(s) 116 to monitor traffic sent between the DMAs 110/CPU cores 112 and the memory 106… The hardware monitors 116 are embedded e.g. inserted in the SOC);
monitoring Direct Memory Access (DMA) to the protection target in real time (see col 4 ln 15-35, the hardware monitors 116 may look at all traffic between the DMAs 110/CPU cores 112 (including traffic passed through programmed I/O 114) and the memory 106) and collecting security logs by executing the security module inserted into the protection target when the embedded system operates (see col 5 ln 10-13, an event logger 120, configured to track the traffic and store information relating to the tracked traffic); and
analyzing whether the embedded system operates normally and whether there is a potential threat based on the collected security logs when operation of the embedded system is terminated (see col 9 ln 5-9, the method includes analyzing the logs to determine circumstances of the violation and generating an associated alert).
Regarding claim 2, Tsidon further teaches the protection target includes a DMA communication path and an MMIO register (see col 3 ln 38-44, the DMAs 110 are configured to access the memory 106 substantially directly… The programmed I/O unit 114 may include a memory-mapped I/O (MMIO), also see col 14 ln 35-38, the tangible memory 720, 725 may be volatile memory (e.g., registers, cache, RAM), non-volatile memory (e.g., ROM, EEPROM, flash memory, etc.)).
Regarding claims 9-10, please refer to the rejection of claims 1-2 since the claimed subject matter is substantially similar. Claims 9-10 recite the apparatus for executing the method of claims 1-2. Tsidon further discloses memory in which at least one program is recorded; and a processor for executing the program (see figure 7, memory 720/725 and CPU 710).
Allowable Subject Matter
Claims 3-8 and 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The known prior arts fail to explicitly disclose “ triggering an exception by detecting a call of a DMA wrapper function based on a Data Watchpoint and Trace (DWT) by executing the security module inserted into the protection target when the embedded system operates; recording a return address and a parameter of the wrapper function that attempts DMA as a security log through an exception handler function when the exception occurs; identifying a source of the DMA through the return address and identifying whether the DMA is abnormal access; and identifying whether there is abnormal access by analyzing whether the parameter falls outside an expected range and matches a normal number of calls” in combination with other limitation found in the independent claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tu et al US 20220374373 discloses a monitoring system for a DMA device coupled to a memory to monitor and debug the memory in real-time
Edery et al US 20210319110 discloses a a secure processing engine to provide real-time protection by accessing the main memory via DMA
Sakurai US 20150339246 discloses an access monitoring unit
Serge et al US Patent No. 8,930,878 discloses a security co-processor for monitoring DMA communication
Miller US 20140068344 discloses filtering data trace information
Flachs et al US 20100161846 discloses direct memory access engine and associated memory mapped input/output (MMIO) registers for the purposes of enqueuing and monitoring DMA commands
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHONG H DANG whose telephone number is (571)272-0470. The examiner can normally be reached Monday-Friday 9:30AM - 6:00PM.
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/PHONG H DANG/Primary Examiner, Art Unit 2184
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