DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s filing on 03/20/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-6, 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Corva et al. (“Corva”, US Pub 2003/0231012).
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Above Fig. 7, 9, from Corva et al. (“Corva”, US Pub 2003/0231012), applied for set of claims ‘1, 5-6’
Regarding independent claim 1, Corva teaches (Fig. 7-9) a system (computer rack or vehicle) comprising:
a load (load);
a circuit (“circuit”) having switches (HS, LS), the circuit coupled to the load (load); and
a controller (other elements “CTRL” in Fig. 7, except for annotated and cited circuit and load) coupled to the circuit,
the controller (CTRL) including
a comparator (current comparator with four terminals “1-4”, as annotated in above Fig. 7, wherein use of switches/transistors/NMOS/PMOS input paired are anticipated) having
a first terminal (“1” receiving 1st signal, such as output of an error amplifier Gm (based on error between feedback voltage “Vfb” of output voltage “Vout” and a reference voltage “Vref”), during pause/sleep mode, which needs to be compensated using ‘Rcomp, Ccomp”, wherein compensated 1st signal’s amplitude lower than 1st signal),
a second terminal (“2” receive 2nd signal RseqiL, via L, which is based on Vsw voltage),
a third terminal (“3 or 3’” receive dynamic biasing circuit’s two current outputs i1 and i2, using two different current generators, wherein i2 (or imax) <i1 (or imin) (i.e., equation 3-5), and i2 is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off), and
a fourth terminal (“4” outputting comparison result based on compensated 1st signal of “1” and 2nd signal of “2”), and
the controller configurable to:
receive a first current at the third terminal of a comparator (“3 or 3’” receive dynamic biasing circuit’s two current outputs i1 and i2, using two different current generators, wherein i2 (or imax) <i1 (or imin), and i2 is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off);
receive a second current at the third terminal of the comparator (“3 or 3’” receive dynamic biasing circuit’s two current outputs i1 and i2, using two different current generators, wherein i2 (or imax) <i1 (or imin), and i2 is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off) responsive to entering a pause mode in which the switches are turned off (any or both HS, LS being off), the second current less than the first current (wherein i2 (or imax) <i1 (or imin); equation 3-5);
receive a first signal at the first terminal of the comparator during the pause mode(“1” receiving 1st signal, such as output of an error amplifier Gm (based on error between feedback voltage “Vfb” of output voltage “Vout” and a reference voltage “Vref”), during pause/sleep mode, which needs to be compensated using ‘Rcomp, Ccomp”, wherein compensated 1st signal’s amplitude lower than 1st signal);
apply a compensation (using Rcomp, Ccomp) to the first signal resulting in a compensated first signal, the compensated first signal having a lower amplitude than the first signal (“1” receiving 1st signal, such as output of an error amplifier Gm (based on error between feedback voltage “Vfb” of output voltage “Vout” and a reference voltage “Vref”), during pause/sleep mode, which needs to be compensated using ‘Rcomp, Ccomp”, wherein compensated 1st signal’s amplitude lower than 1st signal);
receive a second signal at the second terminal of the comparator (“2” receive 2nd signal RseqiL, via L, which is based on Vsw voltage);
provide comparison results at the fourth terminal of the comparator responsive to the compensated first signal and the second signal (“4” outputting comparison result based on compensated 1st signal of “1” and 2nd signal of “2”); and
responsive to the comparator results, provide control signals for the switches (control logic switching HS & LS on/off based on current comparator’s 4th terminals “4” output).
[Additional Examiner’s NOTE: Due to lack of specific claiming, Examiner believes that Corva teaches each and every element, in above claim. Additionally, for further evidence to show how some of the limitations are very well known and established used technique, in the event Applicant has any doubt to speed up prosecution. Examiner recommends the Applicant to consider these art(s) and to amend the claims in such a way so that hopefully the case can be allowed.
Wiersch et al. (US Pub 2020/0106357), can easily be used to reject under 102(a)(1), teaches a circuit (Fig. 1) with switches coupled to a load (Rload); a controller (202, 302) includes a control logic (310) and gate driver (312) used for driving switches (M_HS-LS) with faster vs. slower loop operation during different transient active vs. sleep mode; the controller is further comprises: an error amplifier (EA) with three terminals, wherein output of the error amplifier being from the third terminal of the error amplified is received by one of the first-third inputs (i.e., one of the 1st or 2nd terminals) of a four terminals comparator (comp 306 using NMOS &/or PMOS input pair transistors); a dynamic biasing circuit (316, 308) is received by one of the first-third inputs (i.e., 3rd terminal) of a four terminals comparator (comp 306); and a second compensated signal (i.e., using 304) is received one of the first-third inputs (i.e., other of the 1st or 2nd terminals) of a four terminals comparator (comp 306).
Darmawasakita et al. (US Pub 2014/0132236) can be used as another 102(a)(1) reference, as the art teaches use of plural bias currents (i.e., Fig. 6 describes IDAC register, providing plural programmable variable bias currents) for biasing a comparator (Fig. 3; 104), which compares compensated error signal (Ve received at the + input of 104) with a sensed switching signal used as a feedback (i.e., - input of 104) to provide comparison output (i.e., 104’s output) used by a control logic (102) to drive switch (124), via a driver (122).
Krug et al. (US Pub 2005/0077884) teaches control logic including drivers within (i.e., 156).
Larson et al. (“Larson”, US Pat 4872010) teaches (Fig. 6; col. 4 L3-30) comparator using NMOS or PMOS type input pair transistors.
Colbeck (US Pub 2008/0174342) teaches (Para 1-2, 19-20, 43 and claim 3) Colbeck teaches comparators using differential input stages using NMOS and PMOS.]
Regarding claim 5, Corva teaches
wherein the controller (CTRL) includes a first control loop and a second control loop,
the second control loop is slower than the first control loop (during stand-by/pause/sleep mode Fig. 7 operating in a 2nd loop which is slower vs. during other modes Fig. 7 operating in a 1st loop which is faster; Para 40-41),
the first terminal of the comparator (current comparator’s input terminal “1” receiving 1st signal, such as output of an error amplifier Gm (based on error between feedback voltage “Vfb” of output voltage “Vout” and a reference voltage “Vref”), during pause/sleep mode, which needs to be compensated using ‘Rcomp, Ccomp”, wherein compensated 1st signal’s amplitude lower than 1st signal) coupled to the first control loop (during stand-by/pause/sleep mode Fig. 7 operating in a 2nd loop which is slower vs. during other modes Fig. 7 operating in a 1st loop which is faster; Para 40-41), and
the second terminal of the comparator (“2” receive 2nd signal RseqiL, via L, which is based on Vsw voltage) coupled to the second control loop (during stand-by/pause/sleep mode Fig. 7 operating in a 2nd loop which is slower vs. during other modes Fig. 7 operating in a 1st loop which is faster; Para 40-41).
Regarding claim 6, Corva teaches wherein the controller (CTRL) is configurable to apply the compensation (“1” receiving 1st signal, such as output of an error amplifier Gm (based on error between feedback voltage “Vfb” of output voltage “Vout” and a reference voltage “Vref”), during pause/sleep mode, which needs to be compensated using ‘Rcomp, Ccomp”, wherein compensated 1st signal’s amplitude lower than 1st signal) by generating a negative current (i.e., negative current saturation point or decreased iL which may cross zero, since ZCD is also used in Fig. 7; Para 12-13) or charge to counter an increase in amplitude in the first signal (1st signal, such as output of an error amplifier Gm, which is based on error between feedback voltage “Vfb” of output voltage “Vout” and a reference voltage “Vref”) due to dynamic biasing (Fig. 9 providing dynamic biasing circuit’s two current outputs i1 and i2, using two different current generators, wherein i2 (or imax) <i1 (or imin) (i.e., equation 3-5), and i2 is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off).
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Above Fig. 7, 9, from Corva et al. (“Corva”, US Pub 2003/0231012), applied for set of claims ’16-18’
Regarding independent claim 16, Corva teaches (Fig. 7-9) a circuit (“circuit”) comprising:
an error amplifier have a first terminal, a second terminal, and a third terminal (i.e., an error amplifier Gm providing an error output at 3rd terminal, based on difference between feedback voltage “Vfb” on corresponding (one of 1st or 2nd) terminal of output voltage “Vout” and a reference voltage “Vref” on corresponding (another one of 1st or 2nd ) terminal);
a comparator (current comparator with four terminals “1-4”, as annotated in above Fig. 7, wherein use of switches/transistors/NMOS/PMOS input paired are anticipated) having
a first terminal (1st or 3rd terminal being one of “3” or “1a”, or vice versa each are configured to receive dynamic biasing circuit’s two current outputs i1 and i2, as shown in detail in Fig. 9, using two different current generators, wherein i2 (or Imax) <i1 (or Imin) (i.e., equation 3-5); wherein, i2 or Imax is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off; and each of the two currents is also configured to be compensated (i.e., 1st signal) using feedback loop operation of Fig. 7, depending on which more the circuit is operating, wherein compensation circuits are resistor-capacitor circuit, such as ‘Rcomp, Ccomp’ and ‘ESR, Cout’),
a second terminal (2nd terminal being “2” receiving 2nd signal from the 3rd terminal output of the error amplifier Gm (based on error between feedback voltage “Vfb” of output voltage “Vout” and a reference voltage “Vref”), during pause/sleep mode, which needs to be compensated using ‘Rcomp, Ccomp”, wherein compensated signal’s amplitude lower than 2nd signal),
a third terminal (1st or 3rd terminal being one of “3” or “1a”, or vice versa each are configured to receive dynamic biasing circuit’s two current outputs i1 and i2, as shown in detail in Fig. 9, using two different current generators, wherein i2 (or Imax) <i1 (or Imin) (i.e., equation 3-5); wherein, i2 or Imax is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off; and each of the two currents is also configured to be compensated using feedback loop operation of Fig. 7, depending on which more the circuit is operating, wherein compensation circuits are resistor-capacitor circuit, such as ‘Rcomp, Ccomp’ and ‘ESR, Cout’), and
a fourth terminal (“4” outputting comparison result based on the taught received 1st -2nd signal),
the second terminal of the comparator coupled to the third terminal of the error amplifier (2nd terminal being “2” receiving 2nd signal from the 3rd terminal output of the error amplifier Gm (based on error between feedback voltage “Vfb” of output voltage “Vout” and a reference voltage “Vref”), during pause/sleep mode, which needs to be compensated using ‘Rcomp, Ccomp”, wherein compensated signal’s amplitude lower than 2nd signal);
dynamic biasing circuitry (Fig. 9 providing dynamic biasing circuit’s two current outputs i1 and i2, using two different current generators, wherein i2 (or imax) <i1 (or imin) (i.e., equation 3-5), and i2 is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off) coupled to the third terminal of the comparator (1st or 3rd terminal being one of “3” or “1a”, or vice versa each are configured to receive dynamic biasing circuit’s two current outputs i1 and i2, as shown in detail in Fig. 9, using two different current generators, wherein i2 (or Imax) <i1 (or Imin) (i.e., equation 3-5); wherein, i2 or Imax is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off; and each of the two currents is also configured to be compensated using feedback loop operation of Fig. 7, depending on which more the circuit is operating, wherein compensation circuits are resistor-capacitor circuit, such as ‘Rcomp, Ccomp’ and ‘ESR, Cout’); and
compensation circuitry (resistor-capacitor circuit, such as ‘Rcomp, Ccomp’ and ‘ESR, Cout’) coupled to the first terminal of the comparator and configurable to apply a compensation to a signal at the first terminal of the comparator (1st or 3rd terminal being one of “3” or “1a”, or vice versa each are configured to receive dynamic biasing circuit’s two current outputs i1 and i2, as shown in detail in Fig. 9, using two different current generators, wherein i2 (or Imax) <i1 (or Imin) (i.e., equation 3-5); wherein, i2 or Imax is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off; and each of the two currents is also configured to be compensated using feedback loop operation of Fig. 7, depending on which more the circuit is operating, wherein compensation circuits are resistor-capacitor circuit, such as ‘Rcomp, Ccomp’ and ‘ESR, Cout’).
[Additional Examiner’s NOTE: Due to lack of specific claiming, Examiner believes that Corva teaches each and every element, in above claim. Additionally, for further evidence to show how some of the limitations are very well known and established used technique, in the event Applicant has any doubt to speed up prosecution. Examiner recommends the Applicant to consider these art(s) and to amend the claims in such a way so that hopefully the case can be allowed.
Wiersch et al. (US Pub 2020/0106357), can easily be used to reject under 102(a)(1), teaches a circuit (Fig. 1) with switches coupled to a load (Rload); a controller (202, 302) includes a control logic (310) and gate driver (312) used for driving switches (M_HS-LS) with faster vs. slower loop operation during different transient active vs. sleep mode; the controller is further comprises: an error amplifier (EA) with three terminals, wherein output of the error amplifier being from the third terminal of the error amplified is received by one of the first-third inputs (i.e., one of the 1st or 2nd terminals) of a four terminals comparator (comp 306 using NMOS &/or PMOS input pair transistors); a dynamic biasing circuit (316, 308) is received by one of the first-third inputs (i.e., 3rd terminal) of a four terminals comparator (comp 306); and a second compensated signal (i.e., using 304) is received one of the first-third inputs (i.e., other of the 1st or 2nd terminals) of a four terminals comparator (comp 306).
Darmawasakita et al. (US Pub 2014/0132236) can be used as another 102(a)(1) reference, as the art teaches use of plural bias currents (i.e., Fig. 6 describes IDAC register, providing plural programmable variable bias currents) for biasing a comparator (Fig. 3; 104), which compares compensated error signal (Ve received at the + input of 104) with a sensed switching signal used as a feedback (i.e., - input of 104) to provide comparison output (i.e., 104’s output) used by a control logic (102) to drive switch (124), via a driver (122).
Krug et al. (US Pub 2005/0077884) teaches control logic including drivers within (i.e., 156).
Larson et al. (“Larson”, US Pat 4872010) teaches (Fig. 6; col. 4 L3-30) comparator using NMOS or PMOS type input pair transistors.
Colbeck (US Pub 2008/0174342) teaches (Para 1-2, 19-20, 43 and claim 3) Colbeck teaches comparators using differential input stages using NMOS and PMOS.]
Regarding claim 17, Corva teaches
wherein the signal is a first signal (1st or 3rd terminal being one of “3” or “1a”, or vice versa each are configured to receive dynamic biasing circuit’s two current outputs i1 and i2, as shown in detail in Fig. 9, using two different current generators, wherein i2 (or Imax) <i1 (or Imin) (i.e., equation 3-5); wherein, i2 or Imax is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off; and each of the two currents is also configured to be compensated (i.e., 1st signal) using feedback loop operation of Fig. 7, depending on which more the circuit is operating, wherein compensation circuits are resistor-capacitor circuit, such as ‘Rcomp, Ccomp’ and ‘ESR, Cout’), and the comparator (current comparator with four terminals “1-4”, as annotated in above Fig. 7, wherein use of switches/transistors/NMOS/PMOS input paired are anticipated) is configured to:
receive a first current from the dynamic biasing circuitry at the third terminal of the comparator (1st or 3rd terminal being one of “3” or “1a”, or vice versa each are configured to receive dynamic biasing circuit’s two current outputs i1 and i2, as shown in detail in Fig. 9, using two different current generators, wherein i2 (or Imax) <i1 (or Imin) (i.e., equation 3-5); wherein, i2 or Imax is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off; and each of the two currents is also configured to be compensated using feedback loop operation of Fig. 7, depending on which more the circuit is operating, wherein compensation circuits are resistor-capacitor circuit, such as ‘Rcomp, Ccomp’ and ‘ESR, Cout’);
receive a second current from the dynamic biasing circuitry at the third terminal of the comparator responsive to a pause mode, the second current less than the first current (1st or 3rd terminal being one of “3” or “1a”, or vice versa each are configured to receive dynamic biasing circuit’s two current outputs i1 and i2, as shown in detail in Fig. 9, using two different current generators, wherein i2 (or Imax) <i1 (or Imin) (i.e., equation 3-5); wherein, i2 or Imax is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off; and each of the two currents is also configured to be compensated using feedback loop operation of Fig. 7, depending on which more the circuit is operating, wherein compensation circuits are resistor-capacitor circuit, such as ‘Rcomp, Ccomp’ and ‘ESR, Cout’);
receive the first signal at the first terminal of the comparator during the pause mode (1st or 3rd terminal being one of “3” or “1a”, or vice versa each are configured to receive dynamic biasing circuit’s two current outputs i1 and i2, as shown in detail in Fig. 9, using two different current generators, wherein i2 (or Imax) <i1 (or Imin) (i.e., equation 3-5); wherein, i2 or Imax is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off; and each of the two currents is also configured to be compensated (i.e., 1st signal) using feedback loop operation of Fig. 7, depending on which more the circuit is operating, wherein compensation circuits are resistor-capacitor circuit, such as ‘Rcomp, Ccomp’ and ‘ESR, Cout’);
apply a compensation to the first signal using the compensation circuitry, the compensation resulting in a compensated first signal, the compensated first signal having a lower amplitude than the first signal (1st or 3rd terminal being one of “3” or “1a”, or vice versa each are configured to receive dynamic biasing circuit’s two current outputs i1 and i2, as shown in detail in Fig. 9, using two different current generators, wherein i2 (or Imax) <i1 (or Imin) (i.e., equation 3-5); wherein, i2 or Imax is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off; and each of the two currents is also configured to be compensated (i.e., 1st signal) using feedback loop operation of Fig. 7, depending on which more the circuit is operating, wherein compensation circuits are resistor-capacitor circuit, such as ‘Rcomp, Ccomp’ and ‘ESR, Cout’);
receive a second signal at the second terminal of the comparator (2nd terminal being “2” receiving 2nd signal from the 3rd terminal output of the error amplifier Gm (based on error between feedback voltage “Vfb” of output voltage “Vout” and a reference voltage “Vref”), during pause/sleep mode, which needs to be compensated using ‘Rcomp, Ccomp”, wherein compensated signal’s amplitude lower than 2nd signal); and
provide comparison results at the fourth terminal of the comparator responsive to the compensated first signal and the second signal (“4” outputting comparison result based on the taught received 1st -2nd signal).
Regarding claim 18, Corva teaches
control logic and driver circuitry (control logic anticipated to have drivers to control on/off operation of HS and LS) having a first terminal and a second terminal, the first terminal of the control logic and driver circuitry coupled to the fourth terminal of the comparator (control logic operates based on comparator’s taught 4th terminal output); and
an inductor (L) having a first terminal and a second terminal, the first terminal of the inductor coupled to the second terminal of the control logic and driver circuitry (L’s 1st terminal coupled between HS & LS, which operates based on control logic and driver’s output, thus thru operation connected to 2nd terminal of control logic and drivers), and the second terminal of the inductor coupled to the third terminal of the comparator (L’2 2nd terminal is seen directly connected to 1b directly, along with ‘2-3, 1a’ indirectly thru other operational elements; wherein as described earlier the 1st or 3rd terminal being one of “3” or “1a”, or vice versa each are configured to receive dynamic biasing circuit’s two current outputs i1 and i2, as shown in detail in Fig. 9, using two different current generators, wherein i2 (or Imax) <i1 (or Imin) (i.e., equation 3-5); wherein, i2 or Imax is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off; and each of the two currents is also configured to be compensated (i.e., 1st signal) using feedback loop operation of Fig. 7, depending on which more the circuit is operating, wherein compensation circuits are resistor-capacitor circuit, such as ‘Rcomp, Ccomp’ and ‘ESR, Cout’).
Claims 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Savanth et al. (“Savanth”, US Pub 2018/0150120).
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Above annotated Fig. 1, 3, 5, from Savanth et al. (“Savanth”, US Pub 2018/0150120)
Regarding independent claim 11, Savanth teaches (Fig. 1-14; Para 25-27, 31) a circuit (Fig. 1, 3-5; Fig. 3’s comparator 22, 24’s detail described in Fig. 3 as comparator 34; Para 31) comprising:
a first transistor (NMOS M04 with source, drain and gate terminals) having a first terminal, a second terminal, and a control terminal;
a second transistor (NMOS M05 with source, drain and gate terminals) having a first terminal, a second terminal, and a control terminal, the first and second transistors forming input pair transistors (34’s input pair transistors);
dynamic biasing circuitry (BSEL, M06, M07, M11-12 {a tail-current transistor M06 as a thick gate oxide (TGO) device to allow for better VBIAS control of tail current. In operation, the bias selection bits BxSEL effectively change the mirror ratio between M17 and M6, controlling response speed of the comparator circuit 34 and its quiescent current. A stack of 6 diode-connected voltage threshold transistors (M11-M17) is used for bias generation}; Para 31) including a third transistor (M06 with source, drain and gate terminals) having a first terminal, a second terminal, and a control terminal, the second terminal of the third transistor (M06’s annotated 2nd terminal) coupled to (i.e., M04 & M05’s annotated 1st terminal directly coupled to M06’s annotated 2nd terminal) the first terminals of the first transistor (M04’s annotated 1st terminal) and the second transistor (M04’s annotated 1st terminal); and
compensation circuitry (i.e., threshold voltage devices (28, 30) providing compensated signal Vt of a 1st signal (i.e., input end of 28, 30) used for driving M04’s gate; Para 25-27, 31) coupled to the control terminal of the first transistor (compensated Vt driving M04’s gate), the compensation circuitry configurable to apply a compensation to a signal at the control terminal of the first transistor (compensated Vt driving M04’s gate), the compensation reducing an amplitude of the signal (since 28 & 30 is tunable, thus reducing amplitude of its input signal is expected; Para 26).
[Additional Examiner’s NOTE: Due to lack of specific claiming, Examiner believes that Savanth teaches each and every element, in above claim. Additionally, for further evidence to show how some of the limitations are very well known and established used technique, in the event Applicant has any doubt to speed up prosecution. Examiner recommends the Applicant to consider these art(s) and to amend the claims in such a way so that hopefully the case can be allowed.
Wiersch et al. (US Pub 2020/0106357), can easily be used to reject under 102(a)(1), teaches a circuit (Fig. 1) with switches coupled to a load (Rload); a controller (202, 302) includes a control logic (310) and gate driver (312) used for driving switches (M_HS-LS) with faster vs. slower loop operation during different transient active vs. sleep mode; the controller is further comprises: an error amplifier (EA) with three terminals, wherein output of the error amplifier being from the third terminal of the error amplified is received by one of the first-third inputs (i.e., one of the 1st or 2nd terminals) of a four terminals comparator (comp 306 using NMOS &/or PMOS input pair transistors); a dynamic biasing circuit (316, 308) is received by one of the first-third inputs (i.e., 3rd terminal) of a four terminals comparator (comp 306); and a second compensated signal (i.e., using 304) is received one of the first-third inputs (i.e., other of the 1st or 2nd terminals) of a four terminals comparator (comp 306).
Darmawasakita et al. (US Pub 2014/0132236) can be used as another 102(a)(1) reference, as the art teaches use of plural bias currents (i.e., Fig. 6 describes IDAC register, providing plural programmable variable bias currents) for biasing a comparator (Fig. 3; 104), which compares compensated error signal (Ve received at the + input of 104) with a sensed switching signal used as a feedback (i.e., - input of 104) to provide comparison output (i.e., 104’s output) used by a control logic (102) to drive switch (124), via a driver (122).
Krug et al. (US Pub 2005/0077884) teaches control logic including drivers within (i.e., 156).
Larson et al. (“Larson”, US Pat 4872010) teaches (Fig. 6; col. 4 L3-30) comparator using NMOS or PMOS type input pair transistors.
Colbeck (US Pub 2008/0174342) teaches (Para 1-2, 19-20, 43 and claim 3) Colbeck teaches comparators using differential input stages using NMOS and PMOS.]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Corva (US Pub 2003/0231012), in view of Forbes et al. (“Forbes”, US Pub 2006/0044066).
Regarding claims 7-10, Corva teaches the comparator includes inputs (current comparator with four terminals “1-4”, as annotated in above Fig. 7, wherein use of switches/transistors/NMOS/PMOS input paired are anticipated), and the compensation is performed by a compensation circuitry (current comparator’s 1st or 3rd terminal being one of “3” or “1a”, or vice versa each are configured to receive dynamic biasing circuit’s two current outputs i1 and i2, as shown in detail in Fig. 9, using two different current generators, wherein i2 (or Imax) <i1 (or Imin) (i.e., equation 3-5); wherein, i2 or Imax is in response to controller entering pause/sleep mode in which switches (any one or both of HS, LS) are off; and each of the two currents is also configured to be compensated (i.e., 1st signal) using feedback loop operation of Fig. 7, depending on which more the circuit is operating, wherein compensation circuits are resistor-capacitor circuit, such as ‘Rcomp, Ccomp’ and ‘ESR, Cout’).
However, Corva fails to teach using n-channel metal-oxide semiconductor (NMOS) input pair transistors for the comparing, and PMOS transistor for the compensation circuit (as claimed in claim 7), wherein said transistors have approximately the same gate- source capacitances and gate oxide thickness (as claimed in claim 8); and conversely using PMOS input pair transistors for the comparing, and NMOS transistor for the compensation circuit (as claimed in claim 9), wherein said transistors have approximately the same gate- source capacitances and gate oxide thickness (as claimed in claim 10).
[Additional Examiner’s NOTE: Due to lack of specific claiming, Examiner believes that Corva teaches each and every element, in above claim. Additionally, for further evidence to show how some of the limitations are very well known and established used technique, in the event Applicant has any doubt to speed up prosecution. Examiner recommends the Applicant to consider these art(s) and to amend the claims in such a way so that hopefully the case can be allowed.
Darmawasakita et al. (US Pub 2014/0132236) can be used as another 102(a)(1) reference, as the art teaches use of plural bias currents (i.e., Fig. 6 describes IDAC register, providing plural programmable variable bias currents) for biasing a comparator (Fig. 3; 104), which compares compensated error signal (Ve received at the + input of 104) with a sensed switching signal used as a feedback (i.e., - input of 104) to provide comparison output (i.e., 104’s output) used by a control logic (102) to drive switch (124), via a driver (122).
Krug et al. (US Pub 2005/0077884) teaches control logic including drivers within (i.e., 156).
Larson et al. (“Larson”, US Pat 4872010) teaches (Fig. 6; col. 4 L3-30) comparator using NMOS or PMOS type input pair transistors.
Colbeck (US Pub 2008/0174342) teaches (Para 1-2, 19-20, 43 and claim 3) Colbeck teaches comparators using differential input stages using NMOS and PMOS.]
However, Forbes teaches
using n-channel metal-oxide semiconductor (NMOS) input pair transistors for the comparing (i.e., NMOS 140, 142; Para 28-29, 31-32, 35-36, 39), and PMOS transistor for the compensation circuit (i.e., combined operation of ‘load 182, using PMOS transistors, compensation circuit 185’, operating based on said comparing means input pair transistors operation and bias operation of 184 which includes NMOS transistor, as claimed in claim 7; Para 28-29, 31-32, 35-36, 39), wherein said transistors have approximately the same gate- source capacitances and gate oxide thickness (matched transistors; Para 28-29, 31-32, 35-36, 39; as claimed in claim 8); and conversely
using PMOS input pair transistors for the comparing (i.e., PMOS input pair of transistors; Para 28-29), and NMOS transistor for the compensation circuit (i.e., combined operation of ‘load 182, using NMOS transistors, compensation circuit 185’, operating based on said comparing means input pair transistors operation and bias operation of 184, as claimed in claim 9; Para 28-29, 31-32, 35-36, 39), wherein said transistors have approximately the same gate- source capacitances and gate oxide thickness (matched transistors; Para 28-29, 31-32, 35-36, 39; as claimed in claim 10).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Corva’s system to include use of i) n-channel metal-oxide semiconductor (NMOS) input pair transistors for the comparing, PMOS transistor for the compensation circuit, and said transistors have approximately the same gate- source capacitances and gate oxide thickness; and conversely ii) PMOS input pair transistors for the comparing, NMOS transistor for the compensation circuit, and said transistors have approximately the same gate- source capacitances and gate oxide thickness, as disclosed by Forbes, as doing so would have reduced miller effect with respect to the MOS input pair transistors resulting in increased frequency and transient responses for the comparing means while being compensated, as taught by Forbes (abstract).
Allowable Subject Matter
Claims 2-4, 12-15, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, cited art(s) failed to teach, the system further comprises: “a second load; a second circuit having second switches, the second circuit coupled to the second load; and a second controller coupled to the second circuit, the second controller including a second comparator having a first terminal, a second terminal, a third terminal, and a fourth terminal, and the second controller configurable to: receive a third current at the third terminal of the second comparator; receive a fourth current at the third terminal of the second comparator responsive to entering a pause mode in which the second switches are turned off, the fourth current less than the third current; receive a third signal at the first terminal of the second comparator during the pause mode; apply a second compensation to the third signal resulting in a compensated third signal, the compensated third signal having a lower amplitude than the third signal; receive a fourth signal at the second terminal of the second comparator; provide second comparison results at the fourth terminal of the comparator to the compensated third signal and the fourth signal; and responsive to the second comparison results, provide control signals for the second switches”.
Claims 3-4 depend on claim 2.
Regarding claim 12, cited art(s) failed to teach, “wherein the compensation circuitry includes: a fourth transistor having a first terminal, a second terminal, and a control terminal, the control terminal of the fourth transistor coupled to the control terminal of the first transistor; a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor coupled to the second terminal of the fourth transistor; a sixth transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the sixth transistor coupled to the second terminal of the fifth transistor; and a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor coupled to the first terminal of the fourth transistor and the first terminal of the third transistor, the second terminal of the seventh transistor coupled to the first terminal of the sixth transistor and the control terminals of the fourth transistor and the fifth transistor”.
Claims 13-15 depend on claim 12.
Regarding claim 19, cited art(s) failed to teach, “wherein the comparator includes: a first transistor having a first terminal, a second terminal, and a control terminal; and a second transistor having a first terminal, a second terminal, and a control terminal, the first and second transistors forming an input pair transistors, the dynamic biasing circuitry includes a third transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the third transistor coupled to the first terminals of the first and second transistors, and the compensation circuitry includes: a fourth transistor having a first terminal, a second terminal, and a control terminal ,the control terminal of the fourth transistor coupled to the control terminal of the first transistor; a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor coupled to the second terminal of the fourth transistor; a sixth transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the sixth transistor coupled to the second terminal of the fifth transistor; and a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor coupled to the first terminal of the fourth transistor and the first terminal of the third transistor, the second terminal of the seventh transistor coupled to the first terminal of the sixth transistor and the control terminals of the fourth transistor and the fifth transistor”.
Claim 20 depends on claim 19.
Conclusion
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
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