19063368
DETAILED ACTION
1. This Office Action is taken in response to Applicants’ Amendments and Remarks filed on 8/28/2026 regarding application 19/085,326 filed on 3/20/2025.
Claims 1-19 are pending for consideration.
2. Response to Amendments and Remarks
Applicants’ amendments and remarks have been fully and carefully considered, with the Examiner’s response set forth below.
(1) In view of the amendments and remarks, objections of claims 1-10 have been withdrawn.
(2) In response to the amendments and remarks, an updated claim analysis has been made with additional, new reference(s). Refer to the corresponding sections of the following Office Action for details.
3. Examiner’s Note
(1) In the case of amending the Claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. This will assist in expediting compact prosecution. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.131(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient.
(2) Examiner has cited particular columns/paragraph and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
4. Claims 1-19 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Newly amended claim 1 recites the limitation “a number of valid inactive ZNS zones of each die.”
However, Applicant fails to point out, and the Examiner was not able to identify and locate, the specific passage(s) of the Specification of the current Application provides written descriptions in support of the newly claimed element “valid inactive zones.” As such, the newly added element “valid inactive zones” lacks the support of written descriptions by the Specification of the current Application as requited by 112(a).
Clarifications/corrections are needed.
Claims 2-10 are rejected by virtue of their dependency from claim 1.
Claim 11 suffers from the same deficiency as in claim 1.
Claims 12-19 are rejected by virtue of their dependency from claim 11.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
5. Claims 1-19 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Newly amended claim 1 recites the limitation “a number of valid inactive ZNS zones of each die.”
However, claim 1 is completely silent regarding the scope and definition of “inactive zones.” It is not clear what constitute as, and what does not constitute “inactive zones.” Does it refer to “zones that are erased and do not contain valid data?” Or does it refer to “zones that contain valid data but are idle, i.e., have not been accessed/used for an extended period of time?”
If it refers to “zones that are erased and do not contain valid data,” then it would be the same as the “empty zones” which have already been recited in a separate limitation, resulting in duplicated limitations.
If it refers to “zones that contain valid data but are idle, i.e., have not been accessed/used for an extended period of time,” then what is this extended period of time? One second? One minute? One hour? One day?
Clarifications/corrections are needed.
Claims 2-10 are rejected by virtue of their dependency from claim 1.
Claim 11 suffers from the same deficiency as in claim 1.
Claims 12-19 are rejected by virtue of their dependency from claim 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1, 5-7, 9-11, 15-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US Patent Application Publication 2021/0263674, hereinafter Shin), and in view of Alwala (US Patent Application Publication 2021/0365200).
As to claim 1, Shin teaches A method performed by a memory device comprising memory [A memory system with at least one namespace includes a memory device and a controller. The memory device includes a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided by at least some of the plurality of zones … (abstract); Alwala also teaches this limitation -- as shown in figure 1, where the storage device (102) includes NVM (110) and volatile memory (118)], the memory device coupled to a host device [… a controller including a write buffer with multiple regions, each region corresponding to a respective one of the multiple zones, suitable for: when write data is received from a host … (¶ 0036); Alwala also teaches this limitation -- host, figure 1, 104], the method comprising:
receiving a command to write data the memory device [… a controller including a write buffer with multiple regions, each region corresponding to a respective one of the multiple zones, suitable for: when write data is received from a host … (¶ 0036); Alwala also teaches this limitation -- Each of the data 119 may be associated with a logical address. For example, the NVM 110 may store a logical-to-physical (L2P) mapping table 120 for the storage device 102 associating each data 119 with a logical address. The L2P mapping table 120 stores the mapping of logical addresses specified for data written from the host 104 to physical addresses in the NVM 110 indicating the location(s) where each of the data is stored … When the controller 123 receives a read command or a write command for data 119, the controller checks the cache 122 for the logical-to-physical mapping of each data … (¶ 0031-0033)];
inspecting a die priority list for writing the data to the memory [By way of example but not limitation, the controller 130 can recognize statuses regarding a plurality of channels (or ways) associated with a plurality of memory dies in the memory device 150. The controller 130 may determine the status of each channel or way as a busy status, a ready status, an active status, an idle status, a normal status, and/or an abnormal status. The controller's determination of which channel or way an instruction (and/or data) is delivered through can be associated with a physical block address, e.g., which die(s) the instruction (and/or the data) is to be delivered into … the memory device 150 may include a plurality of dies, each die including a plurality of planes, each plane including the plurality of memory blocks BLK … (¶ 0100-0101); The controller can be configured to determine the victim based on a priority. The priority, determined by the controller, can include: a first highest priority assigned to an implicitly open state zone; a second highest priority assigned to an open state zone associated with the smallest size of data stored in the first and second regions of the write buffer; and a third highest priority assigned to an open state zone associated with the oldest programmed data stored in the first and second regions of the write buffer (¶ 0013);
Alwala more expressively teaches this limitation -- … The controller may also maintain a count of bad blocks for each plane of each die, a count of erase blocks in the spare pool for each die, and a count of bad blocks for each die. Based on these counts, the controller may determine a die sequence indicating the order of dies in which the controller may search for erase blocks in the surplus state (e.g. by scanning the header of each block) … (¶ 0023); The storage device may identify the die sequence to scan for surplus block pairs using various flags and counters … (¶ 0051)], wherein the memory comprises a plurality of dies [By way of example but not limitation, the controller 130 can recognize statuses regarding a plurality of channels (or ways) associated with a plurality of memory dies in the memory device 150. The controller 130 may determine the status of each channel or way as a busy status, a ready status, an active status, an idle status, a normal status, and/or an abnormal status. The controller's determination of which channel or way an instruction (and/or data) is delivered through can be associated with a physical block address, e.g., which die(s) the instruction (and/or the data) is to be delivered into … the memory device 150 may include a plurality of dies, each die including a plurality of planes, each plane including the plurality of memory blocks BLK … (¶ 0100-0101); Alwala also teaches this limitation -- as shown in figure 3, where a plurality of logical dies (0-13) are mapped to their respective physical dies (0-3) in packages 0 and 1 (304)], each die of the plurality of dies comprising a plurality of zones [a plurality of zones as shown in figures 2-4, and 7A-7C; In an embodiment, a memory system with at least one namespace may include a memory device including a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided into at least some of the plurality of zones … (¶ 0007); Alwala also teaches this limitation -- the corresponding “zones” are the “blocks” – as shown in figure 4, where each of the logical dies (0-31) includes multiple planes (406), and each plane includes multiple blocks (408)], wherein the die priority list is associated with the plurality of dies [By way of example but not limitation, the controller 130 can recognize statuses regarding a plurality of channels (or ways) associated with a plurality of memory dies in the memory device 150. The controller 130 may determine the status of each channel or way as a busy status, a ready status, an active status, an idle status, a normal status, and/or an abnormal status. The controller's determination of which channel or way an instruction (and/or data) is delivered through can be associated with a physical block address, e.g., which die(s) the instruction (and/or the data) is to be delivered into … the memory device 150 may include a plurality of dies, each die including a plurality of planes, each plane including the plurality of memory blocks BLK … (¶ 0100-0101); The controller can be configured to determine the victim based on a priority. The priority, determined by the controller, can include: a first highest priority assigned to an implicitly open state zone; a second highest priority assigned to an open state zone associated with the smallest size of data stored in the first and second regions of the write buffer; and a third highest priority assigned to an open state zone associated with the oldest programmed data stored in the first and second regions of the write buffer (¶ 0013);
Alwala more expressively teaches this limitation -- determining a list/sequence of dies using ranking and weighting -- … The controller may also maintain a count of bad blocks for each plane of each die, a count of erase blocks in the spare pool for each die, and a count of bad blocks for each die. Based on these counts, the controller may determine a die sequence indicating the order of dies in which the controller may search for erase blocks in the surplus state (e.g. by scanning the header of each block) … (¶ 0023); Once the controller identifies the first, second, and third die lists, then as represented by block 624, the controller removes any dies from each list that are identified to be in the list of excluded dies described above. Thus, the controller may confirm that all the dies in the three die lists have at least one pair of surplus blocks that may be found. Then, as represented by block 626, the controller identifies a fourth die list from the previous three die lists which indicates the die sequence that the controller may follow when identifying pairs of surplus blocks. The fourth die list may include a rank of each die in ascending order of a weighted average of the first, second, and third die list rankings. For instance, the controller may assign a weightage for each die list, calculate a product of the weightage and the ranking for each die in each die list, add the products together to form a sum of weighted ranks for each die, average the sum of weighted ranks for each die, and then sort the weighted averages in ascending order. For instance, a die which has a weighted average of 1 may be identified to have a higher rank, and thus may be scanned earlier, than a die which has a weighted average of 3.2 …Thus, in this example, the controller may identify the die sequence to be LDI3, LDI 2, LDI1, LDI0, and LDI4. In other words, the controller first scans the erase blocks of logical die 3 for surplus block pairs, followed by the erase blocks in logical die 2, logical die 1, logical die 0, and then lastly logical die 4 (¶ 0060-0064)], and wherein the die priority list is based on:
a number of empty zoned namespace (ZNS) zones of each die [a plurality of zones as shown in figures 2-4, and 7A-7C; A memory system with at least one namespace includes a memory device and a controller. The memory device includes a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided by at least some of the plurality of zones … (abstract); In an embodiment, a memory system with at least one namespace may include a memory device including a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided into at least some of the plurality of zones … (¶ 0007); The memory system may copy valid data stored in the memory block BLK to an empty memory block (or a free block). In the illustrated example of FIG. 1C, the memory system copies the second and the third data {circle around (2)}, {circle around (3)} associated with the second and third application programs APP2, APP3, i.e., valid data, to an empty memory block … (¶ 0060); Referring to FIG. 3, each of the plural zones assigned to plural storage regions of a memory system may be an active zone ACTIVE_ZONE or an inactive zone INACTIVE_ZONE, according to an operation status. The active zone ACTIVE_ZONE may include an open state zone OPEN_ZONE and a closed state zone CLOSED. The inactive zone INACTIVE_ZONE may include an empty zone EMPTY and a full zone FULL. The number of open state zones may be limited based at least on storage capacity of the write buffer as described above. In addition, the number of closed state zones or the number of active zones may be also limited (¶ 0073);
Alwala also teaches number of empty/spare zonesin each die -- Second, as represented by block 620, the controller identifies a second die list including a rank of each die in ascending order of a number of erase blocks in the spare pool. For instance, dies which have a number of spare erase blocks of 2 may be identified to have a higher rank than dies which have a number of spare erase blocks of 20. The ranking is sorted in ascending order since dies with a lower number of spare erase blocks may have experienced more GBBs, and thus a higher likelihood of pairs of single plane good blocks, than dies with a higher number of spare erase blocks. Accordingly, there may be a higher likelihood of forming more erase blocks in each superblock (or more superblocks) from dies with lower numbers of spare erase blocks than from dies with higher numbers of spare erase blocks (¶ 0058)], a number of valid inactive ZNS zones of each die [… In response to the erase command, the memory system may invalidate (or erase) the data associated with the erase command and notify the first application APP1 of the erased state. In the illustrated example of FIG. 1B, the three pieces of first data {circle around (1)} among plural pieces of data in the memory block BLK are invalidated (INVALID), but the second and the third data {circle around (2)}, {circle around (3)} stored by the second and third application programs APP2 and APP3 are still valid. As a size of invalid data in the memory block increases, available storage capacity of the memory system may decrease. Thus, the memory system may perform a garbage collection operation to convert a region in which invalid data is stored into an available region for storing other data. The memory system may copy valid data stored in the memory block BLK to an empty memory block (or a free block). In the illustrated example of FIG. 1C, the memory system copies the second and the third data {circle around (2)}, {circle around (3)} associated with the second and third application programs APP2, APP3, i.e., valid data, to an empty memory block. Invalid data associated with the first application program APP1 might be not copied to the empty memory block … (¶ 0058-0060); Referring to FIG. 3, each of the plural zones assigned to plural storage regions of a memory system may be an active zone ACTIVE_ZONE or an inactive zone INACTIVE_ZONE, according to an operation status. The active zone ACTIVE_ZONE may include an open state zone OPEN_ZONE and a closed state zone CLOSED. The inactive zone INACTIVE_ZONE may include an empty zone EMPTY and a full zone FULL. The number of open state zones may be limited based at least on storage capacity of the write buffer as described above. In addition, the number of closed state zones or the number of active zones may be also limited (¶ 0073);
Alwala also teaches number of inactive/bad zones/blocks -- the corresponding “inactive zones/blocks” are “bad blocks,” which are not to be used, hence inactive -- If the controller determines at block 614 that less than the total number of dies may be added to the list of excluded dies, if any, then the controller may proceed to identify the die sequence of dies to be scanned for surplus block pairs. First, as represented by block 618, the controller identifies a first die list including a rank of each die in descending order of the minimum number of bad blocks for each die. For instance, dies which have a minimum first plane count or second plane count of 17 may be identified to have a higher rank than dies which have a minimum first plane count or second plane count of 10. The ranking is sorted in descending order since dies with higher minimum bad block plane counts may have a higher number of pairs of surplus blocks that may be identified from those dies. For instance, a die having a minimum plane count of 17 bad blocks would include at least 17 pairs of surplus erase blocks, which is more than a die having a minimum plane count of 10 bad blocks (which would include at least 10 pairs of surplus erase blocks) (¶ 0057); Third, as represented by block 622, the controller identifies a third die list including a rank of each die in ascending order of a count of bad blocks for each die. For instance, dies which have a total number of bad blocks (regardless of plane) of 80 may be identified to have a higher rank than dies which have a total number of bad blocks of 200. The ranking is sorted in ascending order since dies with higher bad block counts may have a higher likelihood of pairs of single plane good blocks, as described above (¶ 0059)], and a number of program erase (PE) cycles of each die [… When an application program sends an erase command regarding a full zone or an active zone to the memory system, the memory system may perform an erase operation on a memory block corresponding to a zone associated with the erase command so that the zone can be empty (i.e., erased). The empty zone EMPTY may indicate a specific zone in which a corresponding memory block is erased, i.e., empty (¶ 0073);
Alwala more expressively teaches this limitation -- A controller of the storage device may form superblocks using pairs of erase blocks across different planes of multiple dies. For example, each superblock in a super device including 32 dies may include a maximum of 64 erase blocks or 32 erase block pairs, with the number of erase blocks in each superblock typically being as evenly distributed as possible. Generally, when one of the blocks in one plane of a die becomes a grown bad block (GBB) (e.g. as a result of errors caused by multiple program and erase (P/E) cycles or reads performed on the erase block over time), the other block in the other plane of that die (referred to herein as a single plane good block) may be added directly to the spare pool … (¶ 0020); Each logical die 404 may include multiple planes 406 (i.e. two planes), and each plane 406 may include a group of erase blocks 408 (also referred to as simply blocks). Each erase block 408 may correspond to one of the memory locations 112 of FIG. 1. Each plane 406 may include a number of erase blocks 408 (e.g. 1000 erase blocks or another number) … When the controller 123, 302 groups erase blocks 408 of logical dies 404 into multiple superblocks 412, the controller may attempt to evenly size the superblocks between a minimum (e.g. 56 erase blocks or another number, corresponding to the superblock threshold) and a maximum (e.g. 64 erase blocks or 32 erase block pairs, corresponding to the number of dies N) … For example, the controller may detect that one of the erase blocks 408 has become a GBB in response to an identified error in reading or writing data to the block. GBBs may occur after multiple P/E cycles and reads, which may result in errors in read or written data on the block … (¶ 0042-0043)]; and writing the data to at least one zone of the plurality of zones of the memory based on the die priority list [write operations as shown in figures 1 and 7B; … The controller can be configured to control the memory device to establish first, second and third open zones, and to assign a first region of a write buffer to the first open zone and a second region of the write buffer to the second open zone. When a target zone subject to a new program request is neither the first open zone nor the second open zone, the controller can be configured to determine which one of the first region and the second region is a victim, establish the open state zone associated with the victim as the third open zone, program data associated with the third open zone to a first SLC buffer among the plurality of SLC buffers, and store first data provided with the new program request to one of the first region and the second region, which is determined as the victim, in the write buffer (¶ 0007);
Alwala also teaches this limitation -- surplus blocks from the preferred sequence/list of dies are added to the spare pool for storing new data – Aspects of a storage device including at least one die and a controller are provided that allow superblock formation using surplus block pairs when bad blocks occur … the controller attempts to pair the surplus block with another surplus block from the opposite plane according to a die sequence. If the attempt to pair is successful, the controller adds the pair to the spare pool … (abstract); … The controller may also maintain a count of bad blocks for each plane of each die, a count of erase blocks in the spare pool for each die, and a count of bad blocks for each die. Based on these counts, the controller may determine a die sequence indicating the order of dies in which the controller may search for erase blocks in the surplus state (e.g. by scanning the header of each block) … (¶ 0023); Thus, in this example, the controller may identify the die sequence to be LDI3, LDI 2, LDI1, LDI0, and LDI4. In other words, the controller first scans the erase blocks of logical die 3 for surplus block pairs, followed by the erase blocks in logical die 2, logical die 1, logical die 0, and then lastly logical die 4 (¶ 0064)].
Regarding claim 1, Shin teaches determining priority among a plurality of dies [By way of example but not limitation, the controller 130 can recognize statuses regarding a plurality of channels (or ways) associated with a plurality of memory dies in the memory device 150. The controller 130 may determine the status of each channel or way as a busy status, a ready status, an active status, an idle status, a normal status, and/or an abnormal status. The controller's determination of which channel or way an instruction (and/or data) is delivered through can be associated with a physical block address, e.g., which die(s) the instruction (and/or the data) is to be delivered into … the memory device 150 may include a plurality of dies, each die including a plurality of planes, each plane including the plurality of memory blocks BLK … (¶ 0100-0101); The controller can be configured to determine the victim based on a priority. The priority, determined by the controller, can include: a first highest priority assigned to an implicitly open state zone; a second highest priority assigned to an open state zone associated with the smallest size of data stored in the first and second regions of the write buffer; and a third highest priority assigned to an open state zone associated with the oldest programmed data stored in the first and second regions of the write buffer (¶ 0013)], but does not expressively teach determining the die priority list is based on a number of empty zones of each die, a number of valid inactive zones of each die, and a number of program erase (PE) cycles of each die.
However, Alwala specifically teaches determining the die priority list is based on a number of empty zones of each die [Second, as represented by block 620, the controller identifies a second die list including a rank of each die in ascending order of a number of erase blocks in the spare pool. For instance, dies which have a number of spare erase blocks of 2 may be identified to have a higher rank than dies which have a number of spare erase blocks of 20. The ranking is sorted in ascending order since dies with a lower number of spare erase blocks may have experienced more GBBs, and thus a higher likelihood of pairs of single plane good blocks, than dies with a higher number of spare erase blocks. Accordingly, there may be a higher likelihood of forming more erase blocks in each superblock (or more superblocks) from dies with lower numbers of spare erase blocks than from dies with higher numbers of spare erase blocks (¶ 0058)], a number of valid inactive zones of each die [the corresponding “inactive zones/blocks” are “bad blocks,” which are not to be used, hence inactive -- If the controller determines at block 614 that less than the total number of dies may be added to the list of excluded dies, if any, then the controller may proceed to identify the die sequence of dies to be scanned for surplus block pairs. First, as represented by block 618, the controller identifies a first die list including a rank of each die in descending order of the minimum number of bad blocks for each die. For instance, dies which have a minimum first plane count or second plane count of 17 may be identified to have a higher rank than dies which have a minimum first plane count or second plane count of 10. The ranking is sorted in descending order since dies with higher minimum bad block plane counts may have a higher number of pairs of surplus blocks that may be identified from those dies. For instance, a die having a minimum plane count of 17 bad blocks would include at least 17 pairs of surplus erase blocks, which is more than a die having a minimum plane count of 10 bad blocks (which would include at least 10 pairs of surplus erase blocks) (¶ 0057); Third, as represented by block 622, the controller identifies a third die list including a rank of each die in ascending order of a count of bad blocks for each die. For instance, dies which have a total number of bad blocks (regardless of plane) of 80 may be identified to have a higher rank than dies which have a total number of bad blocks of 200. The ranking is sorted in ascending order since dies with higher bad block counts may have a higher likelihood of pairs of single plane good blocks, as described above (¶ 0059)], and a number of program erase (PE) cycles of each die [A controller of the storage device may form superblocks using pairs of erase blocks across different planes of multiple dies. For example, each superblock in a super device including 32 dies may include a maximum of 64 erase blocks or 32 erase block pairs, with the number of erase blocks in each superblock typically being as evenly distributed as possible. Generally, when one of the blocks in one plane of a die becomes a grown bad block (GBB) (e.g. as a result of errors caused by multiple program and erase (P/E) cycles or reads performed on the erase block over time), the other block in the other plane of that die (referred to herein as a single plane good block) may be added directly to the spare pool … (¶ 0020); Each logical die 404 may include multiple planes 406 (i.e. two planes), and each plane 406 may include a group of erase blocks 408 (also referred to as simply blocks). Each erase block 408 may correspond to one of the memory locations 112 of FIG. 1. Each plane 406 may include a number of erase blocks 408 (e.g. 1000 erase blocks or another number) … When the controller 123, 302 groups erase blocks 408 of logical dies 404 into multiple superblocks 412, the controller may attempt to evenly size the superblocks between a minimum (e.g. 56 erase blocks or another number, corresponding to the superblock threshold) and a maximum (e.g. 64 erase blocks or 32 erase block pairs, corresponding to the number of dies N) … For example, the controller may detect that one of the erase blocks 408 has become a GBB in response to an identified error in reading or writing data to the block. GBBs may occur after multiple P/E cycles and reads, which may result in errors in read or written data on the block … (¶ 0042-0043)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to determine the die priority list is based on a number of empty zones of each die, a number of valid inactive zones of each die, and a number of program erase (PE) cycles of each die, as specifically demonstrated by Alwala, and to incorporate it into the existing scheme disclosed by Shin, because Alwala teaches doing this allow best utilize available spare blocks of the dies and improve the performance of the memory system [Moreover, the spare pool may be limited to a maximum number of erase blocks for each plane of each die (e.g. 14 per plane, or 28 per die) … In such approach where the surplus blocks are not used to form new superblocks, the usable capacity or size of the storage device may effectively be reduced, impacting storage device performance. For example, after a superblock is un-formed as described above, if the number of erase blocks in the spare pool that are available for superblock formation is reduced below the superblock threshold (e.g. 56 erase blocks), these insufficient erase blocks may remain unused in the spare pool, causing the available physical capacity of the storage device to decrease … (¶ 0022)].
As to claim 5, Shin in view of Alwala teaches The method of claim 1, wherein each die of the plurality of dies further comprises a plurality of planes [Shin -- By way of example but not limitation, the controller 130 can recognize statuses regarding a plurality of channels (or ways) associated with a plurality of memory dies in the memory device 150. The controller 130 may determine the status of each channel or way as a busy status, a ready status, an active status, an idle status, a normal status, and/or an abnormal status. The controller's determination of which channel or way an instruction (and/or data) is delivered through can be associated with a physical block address, e.g., which die(s) the instruction (and/or the data) is to be delivered into … the memory device 150 may include a plurality of dies, each die including a plurality of planes, each plane including the plurality of memory blocks BLK … (¶ 0100-0101); Alwala -- as shown in figure 4, where each of the logical dies (0-31) includes multiple planes (406), and each plane includes multiple blocks (408)], the method further comprising, for at least one die of the plurality of dies: inspecting a plane priority list for writing the data to at least one plane of the plurality of planes [Alwala -- A controller of the storage device may form superblocks using pairs of erase blocks across different planes of multiple dies … Generally, when one of the blocks in one plane of a die becomes a grown bad block (GBB) (e.g. as a result of errors caused by multiple program and erase (P/E) cycles or reads performed on the erase block over time), the other block in the other plane of that die (referred to herein as a single plane good block) may be added directly to the spare pool … (¶ 0020-0023); An example of how these weighted averages may be calculated is described as follows, where the controller identifies the following minimum bad block plane counts (or maximum surplus block pairs) … Accordingly, when the controller identifies the first die ranking as described above with respect to block 618, the controller may rank the minimum single bad block plane counts in descending order as follows in Table 2 … (¶ 0061-0062); The die sequence may be based on a first plane count including a first number of single plane bad blocks in the first plane and a second plane count including a second number of single plane bad blocks in the second plane … For example, referring to FIG. 6, the controller may identify the die sequence based on a first die list including die rankings determined based on bad block plane counts, as described above with respect to block 618 … (¶ 0075)], each of the at least one plane comprising a plurality of zones [Shin -- a plurality of zones as shown in figures 2-4, and 7A-7C; By way of example but not limitation, the controller 130 can recognize statuses regarding a plurality of channels (or ways) associated with a plurality of memory dies in the memory device 150. The controller 130 may determine the status of each channel or way as a busy status, a ready status, an active status, an idle status, a normal status, and/or an abnormal status. The controller's determination of which channel or way an instruction (and/or data) is delivered through can be associated with a physical block address, e.g., which die(s) the instruction (and/or the data) is to be delivered into … the memory device 150 may include a plurality of dies, each die including a plurality of planes, each plane including the plurality of memory blocks BLK … (¶ 0100-0101); Alwala -- the corresponding “zones” are the “blocks” – as shown in figure 4, where each of the logical dies (0-31) includes multiple planes (406), and each plane includes multiple blocks (408)]; and writing the data to at least one zone of the plurality of zones of the memory further based on the plane priority list [Shin -- write operations as shown in figures 1 and 7B; … The controller can be configured to control the memory device to establish first, second and third open zones, and to assign a first region of a write buffer to the first open zone and a second region of the write buffer to the second open zone. When a target zone subject to a new program request is neither the first open zone nor the second open zone, the controller can be configured to determine which one of the first region and the second region is a victim, establish the open state zone associated with the victim as the third open zone, program data associated with the third open zone to a first SLC buffer among the plurality of SLC buffers, and store first data provided with the new program request to one of the first region and the second region, which is determined as the victim, in the write buffer (¶ 0007); Alwala -- … The controller may also maintain a count of bad blocks for each plane of each die, a count of erase blocks in the spare pool for each die, and a count of bad blocks for each die. Based on these counts, the controller may determine a die sequence indicating the order of dies in which the controller may search for erase blocks in the surplus state (e.g. by scanning the header of each block) … (¶ 0023); An example of how these weighted averages may be calculated is described as follows, where the controller identifies the following minimum bad block plane counts (or maximum surplus block pairs) … Accordingly, when the controller identifies the first die ranking as described above with respect to block 618, the controller may rank the minimum single bad block plane counts in descending order as follows in Table 2 … Thus, in this example, the controller may identify the die sequence to be LDI3, LDI 2, LDI1, LDI0, and LDI4. In other words, the controller first scans the erase blocks of logical die 3 for surplus block pairs, followed by the erase blocks in logical die 2, logical die 1, logical die 0, and then lastly logical die 4 (¶ 0061-0064)].
As to claim 6, Shin in view of Alwala teaches The method of claim 5, wherein the plane priority list is based on: a number of empty zones of each plane [Alwala -- … Accordingly, when superblocks are un-formed as described above due to bad blocks, the controller may assign the erase blocks 408 that were previously in the superblocks to the spare pool 414 while not exceeding the maximum number of spare erase blocks for each plane 406 and die 404 … (¶ 0048); An example of how these weighted averages may be calculated is described as follows, where the controller identifies the following minimum bad block plane counts (or maximum surplus block pairs), spare pool erase block counts, and total bad block count for five dies (identified by a logical die index (LDI)), which are indicated in Table 1. Although this example assumes that the superblock includes pairs of blocks from five dies, the weighted averages may be similarly calculated to identify the die sequence for any number of dies (e.g. 32 dies as illustrated in FIG. 4) (¶ 0061); Shin -- In an embodiment, a memory system with at least one namespace may include a memory device including a plurality of single-level cell (SLC) buffers and a plurality of memory blocks, wherein each memory block includes a plurality of memory cells, each memory cell storing multi-bit data, and is allocated for a respective one of a plurality of zones, wherein each of the at least one namespace is divided into at least some of the plurality of zones … (¶ 0007); The memory system may copy valid data stored in the memory block BLK to an empty memory block (or a free block). In the illustrated example of FIG. 1C, the memory system copies the second and the third data {circle around (2)}, {circle around (3)} associated with the second and third application programs APP2, APP3, i.e., valid data, to an empty memory block … (¶ 0060)], a number of inactive zones of each plane [Shin -- Referring to FIG. 3, each of the plural zones assigned to plural storage regions of a memory system may be an active zone ACTIVE_ZONE or an inactive zone INACTIVE_ZONE, according to an operation status. The active zone ACTIVE_ZONE may include an open state zone OPEN_ZONE and a closed state zone CLOSED. The inactive zone INACTIVE_ZONE may include an empty zone EMPTY and a full zone FULL. The number of open state zones may be limited based at least on storage capacity of the write buffer as described above. In addition, the number of closed state zones or the number of active zones may be also limited (¶ 0073); Alwala -- … The controller may also maintain a count of bad blocks for each plane of each die, a count of erase blocks in the spare pool for each die, and a count of bad blocks for each die. Based on these counts, the controller may determine a die sequence indicating the order of dies in which the controller may search for erase blocks in the surplus state (e.g. by scanning the header of each block) … (¶ 0023)], and a number of program erase (PE) cycles of each plane [Alwala -- A controller of the storage device may form superblocks using pairs of erase blocks across different planes of multiple dies … Generally, when one of the blocks in one plane of a die becomes a grown bad block (GBB) (e.g. as a result of errors caused by multiple program and erase (P/E) cycles or reads performed on the erase block over time), the other block in the other plane of that die (referred to herein as a single plane good block) may be added directly to the spare pool … (¶ 0020-0023); An example of how these weighted averages may be calculated is described as follows, where the controller identifies the following minimum bad block plane counts (or maximum surplus block pairs) … Accordingly, when the controller identifies the first die ranking as described above with respect to block 618, the controller may rank the minimum single bad block plane counts in descending order as follows in Table 2 … (¶ 0061-0062)].
As to claim 7, Shin in view of Alwala teaches The method of claim 1, further comprising: storing the die priority list in memory [Shin -- By way of example but not limitation, the controller 130 can recognize statuses regarding a plurality of channels (or ways) associated with a plurality of memory dies in the memory device 150. The controller 130 may determine the status of each channel or way as a busy status, a ready status, an active status, an idle status, a normal status, and/or an abnormal status. The controller's determination of which channel or way an instruction (and/or data) is delivered through can be associated with a physical block address, e.g., which die(s) the instruction (and/or the data) is to be delivered into … the memory device 150 may include a plurality of dies, each die including a plurality of planes, each plane including the plurality of memory blocks BLK … (¶ 0100-0101); Alwala -- Each erase block 408 may be associated with metadata, such as a header, which indicates a state of that erase block. For example, the metadata or header of certain erase blocks 408 may indicate that those erase blocks are in a surplus state 416, which represents those erase blocks which are not within the superblocks 412, 504 and not within the spare pool 414 … The metadata of each block may be stored, for example, as data in the NVM 110 (¶ 0047)]; and in response to receiving the write command, inspecting the die priority list to cause the data to be written to the memory based on the die priority list [Alwala -- surplus blocks from the preferred sequence/list of dies are added to the spare pool for storing new data – Aspects of a storage device including at least one die and a controller are provided that allow superblock formation using surplus block pairs when bad blocks occur … the controller attempts to pair the surplus block with another surplus block from the opposite plane according to a die sequence. If the attempt to pair is successful, the controller adds the pair to the spare pool … (abstract); Thus, in this example, the controller may identify the die sequence to be LDI3, LDI 2, LDI1, LDI0, and LDI4. In other words, the controller first scans the erase blocks of logical die 3 for surplus block pairs, followed by the erase blocks in logical die 2, logical die 1, logical die 0, and then lastly logical die 4 (¶ 0064)].
As to claim 9, Shin in view of Alwala teaches The method of claim 1, wherein each zone comprises a planar erase block [Shin -- By way of example but not limitation, the controller 130 can recognize statuses regarding a plurality of channels (or ways) associated with a plurality of memory dies in the memory device 150. The controller 130 may determine the status of each channel or way as a busy status, a ready status, an active status, an idle status, a normal status, and/or an abnormal status. The controller's determination of which channel or way an instruction (and/or data) is delivered through can be associated with a physical block address, e.g., which die(s) the instruction (and/or the data) is to be delivered into … the memory device 150 may include a plurality of dies, each die including a plurality of planes, each plane including the plurality of memory blocks BLK … (¶ 0100-0101); Alwala -- the corresponding “zones” are the “blocks” – as shown in figure 4, where each of the logical dies (0-31) includes multiple planes (406), and each plane includes multiple blocks (408); … The controller may also maintain a count of bad blocks for each plane of each die, a count of erase blocks in the spare pool for each die, and a count of bad blocks for each die. Based on these counts, the controller may determine a die sequence indicating the order of dies in which the controller may search for erase blocks in the surplus state (e.g. by scanning the header of each block) … (¶ 0023); Shin -- ].
As to claim 10, Shin in view of Alwala teaches The method of claim 1, wherein writing the data to the at least one zone of the plurality of zones of the memory based on the die priority list comprises: determining a number of dies that are needed for storing the data; and selecting the number of dies from the plurality of dies according to a top of the die priority list [Alwala -- … The controller may also maintain a count of bad blocks for each plane of each die, a count of erase blocks in the spare pool for each die, and a count of bad blocks for each die. Based on these counts, the controller may determine a die sequence indicating the order of dies in which the controller may search for erase blocks in the surplus state (e.g. by scanning the header of each block) … (¶ 0023); Thus, in this example, the controller may identify the die sequence to be LDI3, LDI 2, LDI1, LDI0, and LDI4. In other words, the controller first scans the erase blocks of logical die 3 for surplus block pairs, followed by the erase blocks in logical die 2, logical die 1, logical die 0, and then lastly logical die 4 (¶ 0064)].
As to claim 11, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 15, it recites substantially the same limitations as in claim 5, and is rejected for the same reasons set forth in the analysis of claim 5. Refer to “As to claim 5” presented earlier in this Office Action for details.
As to claim 16, it recites substantially the same limitations as in claim 6, and is rejected for the same reasons set forth in the analysis of claim 6. Refer to “As to claim 6” presented earlier in this Office Action for details.
As to claim 17, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 7. Refer to “As to claim 7” presented earlier in this Office Action for details.
As to claim 19, it recites substantially the same limitations as in claim 9, and is rejected for the same reasons set forth in the analysis of claim 9. Refer to “As to claim 9” presented earlier in this Office Action for details.
As to claim 20, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
7. Claims 2, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Alwala, and further in view of Kim (US Patent Application Publication 2020/0310968).
Regarding claim 2, Shin in view of Alwala does not teach normalizing the number of empty zones based on a number of total zones of each die.
However, Kim specifically teaches normalizing the number of empty zones based on a number of total zones of each die [percentage is a form of normalization -- For example, the memory system 110 may generate the status information STATUS INFO in the case where the number of free blocks among the plurality of memory blocks 152, 154 and 156 included in the memory device 150 therein is less than a first preset reference. Also, the memory system 110 may update the status information STATUS INFO when the number of free blocks among the plurality of is memory blocks 152, 154 and 156 included in the memory device 150 therein changes by an amount greater than or equal to a second preset reference. Depending on a designer's choice, the first preset reference may be defined as an absolute number of free blocks or may be defined as a percentage of the number of free blocks with respect to the total number of the memory blocks 152, 154 and 156. Similarly, depending on a designer's choice, the second preset reference may be defined as an absolute number of changed free blocks or may be defined as a percentage of changed free blocks with respect to the total number of the memory blocks 152, 154 and 156 … Depending on a designer's choice, the third preset reference may be defined as an absolute number of free blocks or may be defined as a percentage of the number of free blocks with respect to the total number of the memory blocks 152, 154 and 156 … (¶ 0043-0046)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to normalize the number of empty zones based on a number of total zones of each die, as specifically demonstrated by Kim, and to incorporate it into the existing scheme disclosed by Shin in view of Alwala, because Kim teaches doing this allow effective updating the status of the memory device [A memory system may include: a nonvolatile memory device including a plurality of memory blocks; and a controller suitable for checking the number of free blocks among the plurality of memory blocks, generating or updating status information depending on a checking result, and outputting the status information by including the status information in a response to be outputted to a host depending on an operation corresponding to a command inputted from the host (abstract)].
As to claim 12, it recites substantially the same limitations as in claim 2, and is rejected for the same reasons set forth in the analysis of claim 2. Refer to “As to claim 2” presented earlier in this Office Action for details.
8. Claims 3, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Alwala, and further in view of Verhaeghe et al. (US Patent Application Publication 2014/0164674, hereinafter Verhaeghe).
Regarding claim 3, Shin in view of Alwala does not teach normalizing the number of inactive zones based on the number of total zones of each die.
However, Verhaeghe specifically teaches normalizing the number of inactive zones based on the number of total zones of each die [percentage is a form of normalization -- Returning to FIG. 2, in response to a health status command from the host device 100, the controller 110 can calculate usage for all programmable blocks in the memory 120, including spare blocks and even blocks used for caching. The controller 110 then reports back the average percentage used based on the flash's predetermined abilities (i.e., the theoretical limit) … After the command has been verified, the storage device 100 calculates the percentage of average used blocks based on the ability of the particular memory (e.g., NAND) used (i.e., the theoretical limit) (act 430). The storage device 100 then calculates the percentage of bad blocks against the total number of spare blocks available when the memory device 100 was new (act 440) … (¶ 0031)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to normalize the number of inactive zones based on the number of total zones of each die, as specifically demonstrated by Verhaeghe, and to incorporate it into the existing scheme disclosed by Shin in view of Alwala, because Verhaeghe teaches doing this allow effective updating the health status of the memory device [A storage device with a health status check feature is disclosed. In one embodiment, the storage device keeps track of the number of erase cycles performed on the memory of the storage device. The storage device also stores a value of the predicted limit on the number of times that erase cycles can be performed on the memory. In response to a request from a host device for the health status of the memory, the storage device can provide the host device with information about how many erase cycles have been performed on the memory as compared to the predicted limit (abstract)].
As to claim 13, it recites substantially the same limitations as in claim 3, and is rejected for the same reasons set forth in the analysis of claim 3. Refer to “As to claim 3” presented earlier in this Office Action for details.
9. Claims 4, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Alwala, and further in view of Cummins et al. (US Patent 9,348,761, hereinafter Cummins).
Regarding claim 4, Shin in view of Alwala does not teach normalizing a difference between a maximum number of PE cycles of each die and a number of completed PE cycles of each die based on the maximum number of PE cycles of each die.
However, Cummins specifically teaches normalizing a difference between a maximum number of PE cycles of each die and a number of completed PE cycles of each die based on the maximum number of PE cycles of each die [the “remaining lifetime” is the difference between the current erase/write counts and the maximum erase/write counts, and percentage is a form of normalization -- Described in following paragraphs are techniques that may be used in connection with a cache comprising some number of modules or storage devices of limited-write media such as flash memory-based storage devices whereby such techniques provide for placing newly promoted data into cache onto a device having the least wear … Such techniques may leverage a consistent hash to implement device weights which, over time, may be dynamically adjusted based on remaining write capacity or remaining lifetime of the device based on remaining writes for an expected lifetime of that device. Using such techniques herein provides for selecting a particular one of the flash drives determined to have the most remaining write capacity with respect to all the flash drives to extend the amount of wall clock time the flash drives may be actually be used in a system … One piece of information reported by SMART flash memory-based drives is the percentage of lifetime remaining (% lifetime remaining) of a drive. For example, a flash drive may report its % lifetime remaining based on the number of physical erase cycles completed on the drive as a percentage of the maximum physical erase cycles the drive is designed to endure. Generally, the physical drive manufacturer may certify the drive to a certain class of program erase cycles (c10 L50 to c11 L30); The removal technique may be used to predict the endpoint at which a PD may be expected to reach its end of life which may be associated with a 0% lifetime remaining and no replicas. For example, it may be observed that over a time period of 6 months, a PD has gone from a % lifetime remaining of 100% to 50% and the number of replicas for the PD has been reduced from 1000 (for 100% lifetime remaining) to 500 (for 50% lifetime remaining) Based on the foregoing rate of removal of replicas, it may be estimated that the PD has about another 6 months before the number of replicas for the PD goes to zero thereby indicating the PD's end of life or usage … (c17 L37-54)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to normalize a difference between a maximum number of PE cycles of each die and a number of completed PE cycles of each die based on the maximum number of PE cycles, as specifically demonstrated by Cummins, and to incorporate it into the existing scheme disclosed by Shin in view of Alwala, because Cummins teaches doing this allow selecting a particular one of the device determined to have the most remaining write capacity with respect to all the devices [Described in following paragraphs are techniques that may be used in connection with a cache comprising some number of modules or storage devices of limited-write media such as flash memory-based storage devices whereby such techniques provide for placing newly promoted data into cache onto a device having the least wear … Such techniques may leverage a consistent hash to implement device weights which, over time, may be dynamically adjusted based on remaining write capacity or remaining lifetime of the device based on remaining writes for an expected lifetime of that device. Using such techniques herein provides for selecting a particular one of the flash drives determined to have the most remaining write capacity with respect to all the flash drives to extend the amount of wall clock time the flash drives may be actually be used in a system … One piece of information reported by SMART flash memory-based drives is the percentage of lifetime remaining (% lifetime remaining) of a drive. For example, a flash drive may report its % lifetime remaining based on the number of physical erase cycles completed on the drive as a percentage of the maximum physical erase cycles the drive is designed to endure. Generally, the physical drive manufacturer may certify the drive to a certain class of program erase cycles (c10 L50 to c11 L30)].
As to claim 14, it recites substantially the same limitations as in claim 4, and is rejected for the same reasons set forth in the analysis of claim 4. Refer to “As to claim 4” presented earlier in this Office Action for details.
10. Claims 8, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Alwala, and further in view of Jeddeloh (US Patent Application Publication 2010/0192041).
Regarding claim 8, Shin in view of Alwala does not teach identifying an availability of computational bandwidth of the memory device; and determining the die priority list using the availability of computational bandwidth.
However, Jeddeloh specifically teaches identifying an availability of computational bandwidth of the memory device; and determining the die priority list using the availability of computational bandwidth [The memory device 100 may also include a switch 116. In some embodiments, the switch 116 may comprise a matrix switch which might also be referred to as a cross connect switch. The switch 116 is communicatively coupled to the plurality of SCLIs 112 and to the plurality of MVCs 104. The switch 116 is capable of cross-connecting each SCLI to a selected MVC. The host processor(s) 114 may thus access the plurality of memory vaults 102 across the plurality of SCLIs 112 in a substantially simultaneous fashion. This architecture can provide high processor-to-memory bandwidth for modern processor technologies, including multi-core technologies … Such a configuration can enhance memory system bandwidth as a result of the parallelism between the SCLIs 112 and the memory vaults 102 (¶ 0020-0021); FIG. 5 illustrates a manufacturing process that sorts memory after manufacture according to available bandwidth. In operation 510, a number of stacks of memory dies are formed, and in operation 520 a logic die is stacked with the stack of memory dies … In operation 550, the stacks of memory dies are sorted according to available bandwidth as determined by remaining memory capacity of each of the stacks of memory dies. As discussed above, in embodiments without spare memory portions, removal of a portion of the stack can result in the same read bandwidth, but the write bandwidth is slightly diminished. Even in embodiments with spare memory portions, the spare portions may be exceeded, and the resulting stack may have diminished bandwidth. Sorting the stacks of memory dies according to available bandwidth is similar to sorting processors by demonstrated speed after manufacture. Stacks of memory dies can then be matched with a computing system that only requires the particular sorted memory bandwidth … (¶ 0043-0046)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to identify an availability of computational bandwidth of the memory device; and determining the die priority list using the availability of computational bandwidth, as specifically demonstrated by Jeddeloh, and to incorporate it into the existing scheme disclosed by Shin in view of Alwala, because Jeddeloh teaches doing this allow matching the bandwidth of a memory die to a high-speed processor to enhance performance [The memory device 100 may also include a switch 116. In some embodiments, the switch 116 may comprise a matrix switch which might also be referred to as a cross connect switch. The switch 116 is communicatively coupled to the plurality of SCLIs 112 and to the plurality of MVCs 104. The switch 116 is capable of cross-connecting each SCLI to a selected MVC. The host processor(s) 114 may thus access the plurality of memory vaults 102 across the plurality of SCLIs 112 in a substantially simultaneous fashion. This architecture can provide high processor-to-memory bandwidth for modern processor technologies, including multi-core technologies … Such a configuration can enhance memory system bandwidth as a result of the parallelism between the SCLIs 112 and the memory vaults 102 (¶ 0020-0021)].
As to claim 18, it recites substantially the same limitations as in claim 8, and is rejected for the same reasons set forth in the analysis of claim 8. Refer to “As to claim 8” presented earlier in this Office Action for details.
Conclusion
11. Claims 1-19 are rejected as explained above.
12. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE
MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG JEN TSAI whose telephone number is 571-272-4244. The examiner can normally be reached on Monday-Friday, 9-6.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on 571-272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG JEN TSAI/Primary Examiner, Art Unit 2139
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