Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 20, 2025 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshinaga et al (US 2010/0295837).
As per claim 1 Yoshinaga et al depicts in figure 1 and discloses: A display device comprising:
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a plurality of first pixels P arrayed in a first direction;
a plurality of second pixels P arrayed in the first direction and adjacent to the respective first pixels P in a second direction intersecting the first direction;
a first gate line {Figure 1: GATE LINE 0} coupled to a gate of a pixel transistor Tr of each of the first pixels P;
a second gate line {Figure 1: GATE LINES 1-3} coupled to a gate of a pixel transistor Tr of each of the second pixels P;
a drive circuit 2 configured to drive the pixel transistor Tr of the first pixel via the first gate line {Figure 1: GATE LINE 0} and drive the pixel transistor Tr of the second pixel via the second gate line {Figure 1: GATE LINES 1-3}; and
a display region 1 in which the first gate line {Figure 1: GATE LINE 0}, the pixel transistor Tr of the first pixel, the second gate line {Figure 1: GATE LINES 1-3}, and the pixel transistor Tr of the second pixel are arrayed in order in the second direction,
wherein the drive circuit 2 simultaneously turns on the pixel transistor Tr of the first pixel and the pixel transistor Tr of the second pixel, and then sequentially turns off the pixel transistor Tr of the second pixel and the pixel transistor Tr of the first pixel in order { [0106] When the gate driver 2 applies a voltage to (turns on) a given scanning line (referred to as a scanning line .alpha.), the transistors Tr connected to the scanning line .alpha. are turned on, and change can be stored in the capacitor C of each of the pixels P arranged on the scanning line .alpha. (active state). See [0015] also}.
As per claim 2 Yoshinaga et al discloses: The display device according to claim 1, wherein the drive circuit 2 simultaneously controls the first gate line {Figure 1: GATE LINE 0} and the second gate line {Figure 1: GATE LINES 1-3} from a first potential to a second potential higher than the first potential, and then sequentially controls the second gate line {Figure 1: GATE LINES 1-3} and the first gate line {Figure 1: GATE LINE 0} in order from the second potential to the first potential {[0120] As shown in FIG. 3, at the start timing of one frame period (the start timing of a first one horizontal line period), the vertical direction start instruction signal VST and the vertical direction clock VCK are both changed to the H levels. Then, the output Q0 of the first flip-flop 2a-0 is changed to an H level. That is, in this way, the gate line 0, which is the first gate line, is driven.}.
As per claim 4 Yoshinaga et al discloses: A display device comprising:
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a plurality of first pixels P arrayed in a first direction;
a plurality of second pixels P arrayed in the first direction and adjacent to the respective first pixels P in a second direction intersecting the first direction;
a plurality of third pixels arrayed in the first direction and adjacent to the respective second pixels P in the second direction;
a first gate line {Figure 1: GATE LINE 0} coupled to a gate of a pixel transistor Tr of each of the first pixels P;
a second gate line {Figure 1: GATE LINES 1-3} coupled to a gate of a pixel transistor Tr of each of the second pixels P;
a third gate line {Figure 1: GATE LINES 1-3} coupled to a gate of a pixel transistor Tr of each of the third pixels;
a drive circuit 2 configured to drive the pixel transistor Tr of the first pixel via the first gate line {Figure 1: GATE LINE 0}, drive the pixel transistor Tr of the second pixel via the second gate line {Figure 1: GATE LINES 1-3}, and drive the pixel transistor Tr of the third pixel via the third gate line; and
a display region 1 in which the first gate line {Figure 1: GATE LINE 0}, the pixel transistor Tr of the first pixel, the second gate line {Figure 1: GATE LINES 1-3}, the pixel transistor Tr of the second pixel, the third gate line, and the pixel transistor Tr of the third pixel are arrayed in order in the second direction, wherein the drive circuit 2 simultaneously turns on the pixel transistor Tr of the first pixel, the pixel transistor Tr of the second pixel, and the pixel transistor Tr of the third pixel, and then sequentially turns off the pixel transistor Tr of the third pixel, the pixel transistor Tr of the second pixel, and the pixel transistor Tr of the first pixel in order { [0106] When the gate driver 2 applies a voltage to (turns on) a given scanning line (referred to as a scanning line .alpha.), the transistors Tr connected to the scanning line .alpha. are turned on, and change can be stored in the capacitor C of each of the pixels P arranged on the scanning line .alpha. (active state). See [0015] also}.
As per claim 5 Yoshinaga et al discloses: The display device according to claim 4, wherein the drive circuit 2 simultaneously controls the first gate line {Figure 1: GATE LINE 0}, the second gate line {Figure 1: GATE LINES 1-3}, and the third gate line {Figure 1: GATE LINE 0} from a first potential to a second potential higher than the first potential, and then sequentially controls the third gate line, the second gate line {Figure 1: GATE LINES 1-3}, and the first gate line {Figure 1: GATE LINE 0} in order from the second potential to the first potential {[0120] As shown in FIG. 3, at the start timing of one frame period (the start timing of a first one horizontal line period), the vertical direction start instruction signal VST and the vertical direction clock VCK are both changed to the H levels. Then, the output Q0 of the first flip-flop 2a-0 is changed to an H level. That is, in this way, the gate line 0, which is the first gate line, is driven.}.
Allowable Subject Matter
Claims 3 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID D DAVIS whose telephone number is (571)272-7572. The examiner can normally be reached Monday - Friday, 8 a.m. - 4 p.m..
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/DAVID D DAVIS/Primary Examiner, Art Unit 2627
DDD