DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 4, 11 – 13, and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Patent No. 12,204,482 (hereinafter Farjadrad).
As per claim 1, Farjadrad teaches a method comprising: receiving, by a link layer module (Farjadrad; Figure 1 Item 124) of a base die in a chiplet (Farjadrad; Figure 1 Item 106), signals in a memory controller (MC) interface format from MCs (Farjadrad; Figure 1 Items 118 and 120) of the base die, wherein the signals correspond to memory channels of the chiplet (Farjadrad; Col 5 Lines 51 – 57); mapping, by the link layer module, the signals to a signal in a die-to-die (D2D) packet format (Farjadrad; Figure 4, Figure 7, Col 2 Line 59 – Col 3 Line 6, Col 6 Lines 28 – 32) based on a mapping ratio between the MCs and the link layer module (Farjadrad; Figure 4, Figure 6, Figure 7, Col 6 Lines 16 – 26); and sending the signal in the D2D packet format from the link layer module to a D2D module (Farjadrad; Figure 1 Item 119) of the base die, wherein the chiplet is disposed on an interface or substrate (Farjadrad; Figure 1 Item 102) of a superchip.
As per claims 2 and 12, Farjadrad also teaches transferring, via the D2D module, the signal from the chiplet to another chiplet (Farjadrad; Figure 1 Item 104) of the superchip (Farjadrad; Col 5 Lines 36 – 43).
As per claims 3 and 13, Farjadrad also teaches wherein the MCs are a subset of a plurality of MCs of the base die (Farjadrad; Col 7 Lines 37 – 41), and the link layer module is one of a plurality of link layer modules of the base die (Farjadrad; Col 7 Lines 37 – 41).
As per claim 4, Farjadrad also teaches wherein the D2D packet format comprises a universal chiplet interconnect express (UCIe) (Farjadrad; Col 2 Lines 59 – 64), and the D2D module comprises a UCIe module (Farjadrad; Col 2 Lines 59 – 64).
As per claims 11 and 20, Farjadrad teaches a base die of a chiplet (Farjadrad; Figure 1 Item 106) comprising: memory controllers (MCs) (Farjadrad; Figure 1 Items 118 and 120); a die-to-die (D2D module (Farjadrad; Figure 1 Item 119); and a link layer module (Farjadrad; Figure 1 Item 124) configured to: receive signals in an MC interface format from the MCs, wherein the signals correspond to memory channels in the chiplet (Farjadrad; Col 5 Lines 51 – 57); map the signals to a signal in a die-to-die (D2D) packet format (Farjadrad; Figure 4, Figure 7, Col 2 Line 59 – Col 3 Line 6, Col 6 Lines 28 – 32) based on a mapping ratio between the MCs and the link layer module (Farjadrad; Figure 4, Figure 6, Figure 7, Col 6 Lines 16 – 26); and send the signal in the D2D packet format to the D2D module (Farjadrad; Figure 1 Item 119).
Allowable Subject Matter
Claims 5 – 10 and 14 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 5 – 10 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination wherein mapping the signals comprises: optimizing the signals for D2D transmission by a protocol adapter of the link layer module; packing, by the protocol adapter, the signals into containers sized based on the MC interface format; subdividing, by the protocol adapter, the containers into sub-containers based on a clock domain crossing (CDC) buffer format; grouping, by a CDC module of the link layer module, the sub-containers and converting the grouped sub-containers into a single data unit; and encapsulating, by a format de-mapping module of the link layer module, the single data unit into a field of the D2D packet format, as required by dependent claim 5, in combination with the other claimed limitations (emphasis added). The prior art of record teaches mapping the MC signals to a D2D packet format (Farjadrad; Figure 4, Figure 7, Col 2 Line 59 – Col 3 Line 6, Col 6 Lines 28 – 32), but does not teach the specific mapping steps required by dependent claim 5.
Claims 6 – 10 would also be allowable because of their dependence, either directly or indirectly, upon allowable dependent claim 5.
Claims 14 – 19 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination wherein, in mapping the signals, the link layer module is configured to: optimize the signals for D2D transmission by a protocol adapter of the link layer module; pack, by the protocol adapter, the signals into containers sized based on the MC interface format; subdivide, by the protocol adapter, the containers into sub-containers based on a clock domain crossing (CDC) buffer format; group, by a CDC module of the link layer module, the sub-containers and convert the grouped sub-containers into a single data unit; and encapsulate, by a format de-mapping module of the link layer module, the single data unit into a field of the D2D packet format, as required by dependent claim 14, in combination with the other claimed limitations (emphasis added). The prior art of record teaches a link layer module (Farjadrad; Figure 1 Item 124) mapping the MC signals to a D2D packet format (Farjadrad; Figure 4, Figure 7, Col 2 Line 59 – Col 3 Line 6, Col 6 Lines 28 – 32), but does not teach the specific mapping steps required by dependent claim 14.
Claims 15 – 19 would also be allowable because of their dependence, either directly or indirectly, upon allowable dependent claim 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
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/RICHARD B FRANKLIN/ Examiner, Art Unit 2181
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