Detailed Action
Status of Claims
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claims 1-20 are rejected.
This Action is Non-Final.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/20/2025 and 10/22/2025,the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ayyapureddi (US Patent Application Pub No: 20250061070 A1) in view of Farjadrad (US Patent No: 12,602,531 B1).
As per claim 1,Ayyapureddi teaches a modular high-bandwidth memory (HBM) system [Fig.1, A memory device (e.g., a high-bandwidth (HBM) memory device)….], comprising:
a compute die including a memory controller [Fig.3, the memory-side control logic 310.];
one or more die-to-die (D2D) channels coupled to the compute die [Fig.4; Paragraphs 0028-0029, The memory die 400 includes channels 402 that are further subdivided into multiple pseudo channels 404.]; and
one or more HBM chiplets coupled to the one or more, channels [Abstract, Paragraphs 0014;0016, Each channel provides access to an independent set of storage of the HBM device (e.g., requests from one channel do not access data associated with a different channel), and the channels can be operated independently without needing to be synchronized.], and configured to: receive a memory access request, and process the memory access request [Paragraph 0021, The memory die can include circuitry to determine whether to route a command received over the channel's command interface to the first set of memory banks or the second set of memory banks.], or
forward the memory access request to a subsequent HBM chiplet [Paragraph 0043,…the interface die 506 can receive commands from a memory controller (e.g., memory controller 306 of FIG. 3) and transmit the commands to the memory dies 504 such that the data can be communicated from the memory dies with a higher bandwidth.].
Ayyapureddi does not explicitly disclose die-to-die channels.
Farjadrad discloses die-to-die channels [Abstract, claim 1,…. port comprising a die-to-die (D2D) interface to couple to an IC device, the first port comprising circuitry to transfer information via a packet-based protocol between the IC base die and the IC device;….].
It would have been obvious one ordinary skill in the art before the effective filling, date of the claimed invention, to include Farjadrad’s memory chiplet into Ayyapureddi’s high-bandwidth memory (HBM) device for the benefit of the mold reduces latency or delay in fully processing data by multiple chips, thus increasing yields for larger chips, and reducing overall costs for chip manufacturers (Farjadrad, col.1,ll.40-50) to obtain the invention as specified in claim 1.
As per claim 2, Ayyapureddi and Farjadrad teach all the limitations of claim 1 above, where Ayyapureddi teaches, a modular HBM system, wherein the one or more HBM chiplets [Ayyapureddi, Fig.1, A memory device (e.g., a high-bandwidth (HBM) memory device)….], are configured to: process the memory access request in case the memory access request corresponds to a local memory address range [Ayyapured, claim 1, A high-bandwidth memory (HBM) device comprising: a plurality of channels each associated with a command address bus, each channel subdivided into a plurality of pseudo channels each associated with a data bus;….].
As per claim 3, Ayyapureddi and Farjadrad teach all the limitations of claim 1 above, where Ayyapureddi teaches, a modular HBM system, wherein the one or more HBM chiplets are configured to: forward the memory access request to the subsequent HBM chiplet in case the memory access request does not correspond to a local memory address range [Ayyapureddi ,Paragraph 0043,…the interface die 506 can receive commands from a memory controller (e.g., memory controller 306 of FIG. 3) and transmit the commands to the memory dies 504 such that the data can be communicated from the memory dies with a higher bandwidth.].
As per claim 4, Ayyapureddi and Farjadrad teach all the limitations of claim 1 above, where Ayyapureddi and Farjadrad teach, a modular HBM system [Ayyapureddi, Fig.1, A memory device (e.g., a high bandwidth (HBM) memory device)….], wherein the one or more HBM chiplets are connected in a daisy-chain configuration [Farjadrad, col.8,ll.33-46, …. includes silicon bridges 1202 and 1204 to connect adjacent memory devices together in a daisy-chained manner,….].
As per claim 5, Ayyapureddi and Farjadrad teach all the limitations of claim 4 above, where Ayyapureddi and Farjadrad teach, a modular HBM system [Ayyapureddi, Fig.1, A memory device (e.g., a high-bandwidth (HBM) memory device)….], wherein the memory controller in the compute die is configured to determine a number of nodes connected in the daisy-chain configuration by issuing a discovery command with a node number that is decremented by each of the one or more HBM chiplets connected in the daisy-chain configuration [Farjadrad, col.8,ll.33-46, …. includes silicon bridges 1202 and 1204 to connect adjacent memory devices together in a daisy-chained manner,….].
As per claim 6, Ayyapureddi and Farjadrad teach all the limitations of claim 5 above, where Ayyapureddi and Farjadrad teach, a modular HBM system [Ayyapureddi, Fig.1, A memory device (e.g., a high-bandwidth (HBM) memory device)….], wherein in a case in which the node number of the discovery command is equal to 0, the discovery command is processed locally [Farjadrad, col.4,ll.1-23,…, the logic base die 204 incorporated in the memory device 108 is manufactured in accordance with a logic process that incorporates node feature sizes similar to those of the first IC chip and the second IC chip, but with a much smaller overall size and footprint.].
As per claim 7, Ayyapureddi and Farjadrad teach all the limitations of claim 5 above, where Ayyapureddi and Farjadrad teach, a modular HBM system [Ayyapureddi, Fig.1, A memory device (e.g., a high-bandwidth (HBM) memory device)….], wherein in a case in which the node number of the discovery command is greater than 0, the discovery command is forwarded to a subsequent HBM chiplet in the daisy-chain configuration [Farjadrad, col.4,ll.1-23,…, the logic base die 204 incorporated in the memory device 108 is manufactured in accordance with a logic process that incorporates node feature sizes similar to those of the first IC chip and the second IC chip, but with a much smaller overall size and footprint.].
As per claim 8, Ayyapureddi and Farjadrad teach all the limitations of claim 5 above, where Ayyapureddi and Farjadrad teach, a modular HBM system [Ayyapureddi, Fig.1, A memory device (e.g., a high-bandwidth (HBM) memory device)….], wherein in a case in which the node number of the discovery command is an invalid value, an error message is transmitted to the compute die, enabling the compute die to determine the total number of nodes in the daisy-chain configuration [Farjadrad, col.8,ll.33-46, …. includes silicon bridges 1202 and 1204 to connect adjacent memory devices together in a daisy-chained manner,….].
As per claim 9, Ayyapureddi and Farjadrad teach all the limitations of claim 1 above, where Ayyapureddi teaches, a modular HBM system [Ayyapureddi, Fig.1, A memory device (e.g., a high-bandwidth (HBM) memory device)….], wherein the one or more HBM chiplets are connected in a network-grid configuration, and wherein each of the one or more HBM chiplets connected in the network-grid configuration is configured to forward the memory access request along multiple routing paths [Ayyapureddi ,Paragraph 0043,…the interface die 506 can receive commands from a memory controller (e.g., memory controller 306 of FIG. 3) and transmit the commands to the memory dies 504 such that the data can be communicated from the memory dies with a higher bandwidth.].
As per claim 10, Ayyapureddi and Farjadrad teach all the limitations of claim 9 above, where Ayyapureddi teaches, a modular HBM system [Ayyapureddi, Fig.1, A memory device (e.g., a high-bandwidth (HBM) memory device)….], wherein the one or more HBM chiplets connected in the network-grid configuration include a built-in compute die configured to perform a compute-in-memory (CIM) operation [Ayyapureddi Paragraphs 0026-0029, …the control logic 310 can decode signals from the memory controller 306 and perform operations at the memory 312.].
As per claims 11-20, claims 11-20 are rejected in accordance to the same rational and reasoning as the above claims 1-10 above, wherein claims 111-20 are the method claims for the system of claims 1-10.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
References Considered Pertinent but not relied upon
Dabral (US Patent Application Pub. No: 20260096483 A1) teaches memory system and methods of fabrication are described in which memory capacity and/or bandwidth can be expanded. In some implementations expansion may be accomplished with inclusion of custom buffer base dies, or other suitable components including network routing connecting multiple memory die stacks. In some implementations expansion may be accomplished with integration of vertically oriented memory die stacks.
Kim et al.(US Patent Application Pub. No: 20220189934 A1) teaches the technology relates to an integrated circuit (IC) package in which an interconnection interface chiplet and/or interconnection interface circuit are relocated, partitioned, and/or decoupled from a main or core IC die and/or high-bandwidth memory (HBM) components in an integrated component package.
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/GETENTE A YIMER/Primary Examiner, Art Unit 2181
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