The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination in this application (19/085,704) filed on March 20, 2025.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claims 1-20 are pending for consideration.
Drawings
The drawings submitted on March 20, 2025 have been considered and accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1, 11, 12, 14, 15 and 20 are rejected under 35 U.S.C. 103(a) as being unpatentable by Mora Porta et al. (US PGPUB 2024/0028400) (hereinafter Mora Porta), in view of Ji et al. (US PGPUB 2025/0094334 hereinafter referred to as Ji).
As per independent claim 1, Mora Porta discloses a system comprising: a memory device; and a processing device, operatively coupled to the memory device, configured to perform operations comprising: monitoring a set of periodic read counts for a set of higher-level cell blocks of the memory device [(Paragraphs 0044 and 0056; Figs. 1 and 5) where Mora Porta teaches where FIG. 5A shows a logic diagram 500 which may be implemented in the transaction monitor 114 of FIG. 4. Amongst other components the logic diagram 500 includes a time slot length 502, a time slot tracker 504, a read counter(s) 506, a write counter(s) 508, and a threshold 510. The time slot length 502 may set the length of a time slot 204, such as 1500 cycles in the example above. The time slot tracker 504 may be used to track progress through the time slot 204 (e.g., the number of elapsed cycles), so that a RESET_COUNTERS signal is generated when the time slot 204 ends. The RESET_COUNTERS signal may cause the read counter 506 and the write counter 508 to be reset (e.g., to zero) for a subsequent time slot 204. The read counter 506 may be configured to track the total number of read transactions from a processing resource 108 for a time slot 204. The write counter 508 may be configured to track the total number of write transactions from the processing resource 108 for the time slot 204. The threshold(s) 510 may be used to set the threshold(s) used to enforce the bandwidth allocation(s) for the processing resource 108. In the example shown, the threshold(s) 510 provide a Max number of transactions for the time slot 204 to correspond to the claimed limitation], each periodic read count of the set of periodic read counts being reset to an initial value after a predetermined period of time [(Paragraphs 0044 and 0056; Figs. 1 and 5) where Mora Porta teaches where FIG. 5A shows a logic diagram 500 which may be implemented in the transaction monitor 114 of FIG. 4. Amongst other components the logic diagram 500 includes a time slot length 502, a time slot tracker 504, a read counter(s) 506, a write counter(s) 508, and a threshold 510. The time slot length 502 may set the length of a time slot 204, such as 1500 cycles in the example above. The time slot tracker 504 may be used to track progress through the time slot 204 (e.g., the number of elapsed cycles), so that a RESET_COUNTERS signal is generated when the time slot 204 ends. The RESET_COUNTERS signal may cause the read counter 506 and the write counter 508 to be reset (e.g., to zero) for a subsequent time slot 204. The read counter 506 may be configured to track the total number of read transactions from a processing resource 108 for a time slot 204. The write counter 508 may be configured to track the total number of write transactions from the processing resource 108 for the time slot 204. The threshold(s) 510 may be used to set the threshold(s) used to enforce the bandwidth allocation(s) for the processing resource 108. In the example shown, the threshold(s) 510 provide a Max number of transactions for the time slot 204 to correspond to the claimed limitation]; and for an individual higher-level cell block of the set of higher-level cell blocks: accessing, from the set of periodic read counts, an individual periodic read count of the individual higher-level cell block; determining whether the individual periodic read count is greater than a threshold value; and in response to determining that the individual periodic read count is greater than the threshold value, causing data to be transferred from the individual higher-level cell block to one or more lower-level cell blocks of the memory device [(Paragraphs 0038-0042 and 0066-0069; Figs. 1 and 4) where Mora Porta teaches where to correspond to the claimed limitation].
Mora Porta does not appear to explicitly disclose for an individual higher-level cell block of the set of higher-level cell blocks: accessing, from the set of periodic read counts, an individual periodic read count of the individual higher-level cell block; determining whether the individual periodic read count is greater than a threshold value; and in response to determining that the individual periodic read count is greater than the threshold value, causing data to be transferred from the individual higher-level cell block to one or more lower-level cell blocks of the memory device.
However, Ji discloses for an individual higher-level cell block of the set of higher-level cell blocks: accessing, from the set of periodic read counts, an individual periodic read count of the individual higher-level cell block; determining whether the individual periodic read count is greater than a threshold value [(Paragraphs 0044, 0056-0062, 0081 and 0110) wherein Ji discloses the read count of the first memory block BLK1 may reach a first threshold count (th_cnt1) as the read request including the tenth logical address LA10 is repeatedly received from the host 400. When the read count of the first memory block (BLK1) is equal to or greater than the first threshold count (th_cnt1), the operation controller 230 may control the memory device 100 to perform a test read operation of reading data stored in at least one page included in the first memory block BLK1 to correspond to the claimed limitation]; and in response to determining that the individual periodic read count is greater than the threshold value, causing data to be transferred from the individual higher-level cell block to one or more lower-level cell blocks of the memory device [(Paragraphs 0044, 0056-0062, 0081 and 0110) wherein Ji discloses where the read count of the first memory block (BLK1) may reach the second threshold count (th_cnt2) as the read request including the tenth logical address (LA10) is repeatedly received. The operation controller 230 may control the memory device 100 to perform the test read operation of reading the data stored in the first memory block (BLK1) when the read count of the first memory block (BLK1) is equal to or greater than the second threshold count (th_cnt2). When the number of error bits included in the data read from the first memory block (BLK1) is greater than the first threshold number of bits, the operation controller 230 may control the memory device 100 to perform the refresh operation of copying the first to tenth data (Data1 to Data10) stored in the first memory block (BLK1) to the ninth memory block (BLK9). In an embodiment, the first memory block (BLK1) and the ninth memory block (BLK9) may be included in different super blocks. In an embodiment, memory cells included in the ninth memory block (BLK9) may store bits of the number less than those of memory cells included in the first memory block (BLK1). For example, the memory cells included in the ninth memory block (BLK9) may be single level cells (SLCs), and the memory cells included in the first memory block BLK1 may be triple level cells (TLCs) to correspond to the claimed limitation].
Mora Porta and Ji are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Mora Porta and Ji before him or her, to modify the method of Mora Porta to include the read count operations of Ji because it will enhance data access.
The motivation for doing so would be [“control a priority of the refresh operation on any page among the pages of the first memory block, based on the number of times logical addresses corresponding to the pages of the first memory block that are received from the host” (Paragraph 0007 by Ji)].
Therefore, it would have been obvious to combine Mora Porta and Ji to obtain the invention as specified in the instant claim.
As per dependent claim 11, Ji discloses wherein the operations comprise: receiving, from a host system, a request to read a set of blocks of the memory device, the set of blocks including the individual higher-level cell block, the accessing of the individual periodic read count being performed in response to the request [(Paragraphs 0007-0009 and 0039-0041) where in response to a read request from a host, to control the memory device to read data stored in a first page corresponding to a first logical address included in the read request, update a read count of the first memory block including the first page, and perform a refresh operation of copying data stored in pages of the first memory block to the second memory block based on the read count of the first memory block to correspond to the claimed limitation].
As per dependent claim 12, Mora Porta discloses wherein the accessing of the individual periodic read count is performed periodically based on the predetermined period of time [(Paragraphs 0044 and 0056; Figs. 1 and 5) where Mora Porta teaches where FIG. 5A shows a logic diagram 500 which may be implemented in the transaction monitor 114 of FIG. 4. Amongst other components the logic diagram 500 includes a time slot length 502, a time slot tracker 504, a read counter(s) 506, a write counter(s) 508, and a threshold 510. The time slot length 502 may set the length of a time slot 204, such as 1500 cycles in the example above. The time slot tracker 504 may be used to track progress through the time slot 204 (e.g., the number of elapsed cycles), so that a RESET_COUNTERS signal is generated when the time slot 204 ends. The RESET_COUNTERS signal may cause the read counter 506 and the write counter 508 to be reset (e.g., to zero) for a subsequent time slot 204. The read counter 506 may be configured to track the total number of read transactions from a processing resource 108 for a time slot 204. The write counter 508 may be configured to track the total number of write transactions from the processing resource 108 for the time slot 204. The threshold(s) 510 may be used to set the threshold(s) used to enforce the bandwidth allocation(s) for the processing resource 108. In the example shown, the threshold(s) 510 provide a Max number of transactions for the time slot 204 to correspond to the claimed limitation].
As per dependent claim 15, Mora Porta discloses wherein the operations are performed periodically based on the predetermined period of time [(Paragraphs 0044 and 0056; Figs. 1 and 5) where Mora Porta teaches where FIG. 5A shows a logic diagram 500 which may be implemented in the transaction monitor 114 of FIG. 4. Amongst other components the logic diagram 500 includes a time slot length 502, a time slot tracker 504, a read counter(s) 506, a write counter(s) 508, and a threshold 510. The time slot length 502 may set the length of a time slot 204, such as 1500 cycles in the example above. The time slot tracker 504 may be used to track progress through the time slot 204 (e.g., the number of elapsed cycles), so that a RESET_COUNTERS signal is generated when the time slot 204 ends. The RESET_COUNTERS signal may cause the read counter 506 and the write counter 508 to be reset (e.g., to zero) for a subsequent time slot 204. The read counter 506 may be configured to track the total number of read transactions from a processing resource 108 for a time slot 204. The write counter 508 may be configured to track the total number of write transactions from the processing resource 108 for the time slot 204. The threshold(s) 510 may be used to set the threshold(s) used to enforce the bandwidth allocation(s) for the processing resource 108. In the example shown, the threshold(s) 510 provide a Max number of transactions for the time slot 204 to correspond to the claimed limitation].
As for independent claims 14 and 20, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Claims 3 and 17 are rejected under 35 U.S.C. 103(a) as being disclosed by Mora Porta in view of Ji, as applied to claim 1, and further in view of Kato et al. (US PGPUB 2014/0115244 hereinafter referred to as Kato).
As per dependent claim 3, Mora Porta/Ji discloses the system according to claim 1.
Mora Porta/Ji does not appear to explicitly disclose wherein the causing of the data to be transferred from the individual higher-level cell block to the one or more lower-level cell blocks comprises: marking the individual higher-level cell block as a candidate for higher-level cell-to-lower-level cell block data transfer.
However, Maybee discloses wherein the causing of the data to be transferred from the individual higher-level cell block to the one or more lower-level cell blocks comprises: marking the individual higher-level cell block as a candidate for higher-level cell-to-lower-level cell block data transfer [(Paragraphs 0036-0037; FIGs. 1-3) where the eviction list 119 of the L1 cache 110, to identify data blocks that may be a candidate for transfer from the L1 cache 110 to the L2 cache 121. The data blocks may be selected from the L1 cache 110 in the form of one or more data chunks and subsequently added to the L2 MRU list 207 of the L2 cache 121 to correspond to the claimed limitation].
Mora Porta/Ji and Maybee are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Mora Porta/Ji and Maybee before him or her, to modify the method of Mora Porta/Ji to include the marking of candidate blocks for data transfer of Maybee because it will enhance data access.
The motivation for doing so would be [“ improve performance” (Paragraph 0002 by Maybee)].
Therefore, it would have been obvious to combine Mora Porta/Ji and Maybee to obtain the invention as specified in the instant claim.
As for dependent claim 17, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
Claims 5 and 6 are rejected under 35 U.S.C. 103(a) as being disclosed by Mora Porta in view of Ji, as applied to claim 1, and further in view of Kanno et al. (US 11,704,069 hereinafter referred to as Kanno).
As per dependent claim 5, Mora Porta/Ji discloses the system according to claim 1.
Mora Porta/Ji does not appear to explicitly disclose wherein each higher-level cell block is a quad-level cell (QLC) block.
However, Kanno discloses wherein each higher-level cell block is a quad-level cell (QLC) block [(Column 31, lines 55-67 and Column 32, lines 1-20) where the controller 4 copies the write data already written to one first storage region (QLC block) managed as the first zone from the one first storage region (QLC block) to the SLC buffer 201 and the like, and thereby sets this one first storage region (QLC block) to the state in which the valid data is not stored. After the total of the data size of the already written write data (i.e., the data size of the copied write data), the data size of remaining write data un-transferred to the internal buffer 161, of the plurality of write data associated with the received first write commands each specifying the first zone, and the data size of the subsequent write data associated with the plurality of subsequent first write commands specifying the first zone, reaches the capacity of the first zone, the controller 4 transfers the remaining write data and the subsequent write data from the write buffer 51 of the host 2 to the internal buffer 161. Then, the controller 4 may open this first storage region (QLC block), write the written write data copied to the SLC buffer 201 and the like, the remaining write data transferred to the internal buffer 161, and the subsequent write data to this first storage region, and thereby set this first storage region to the state in which the whole first storage region is filled with the data to correspond to the claimed limitation].
Mora Porta/Ji and Kanno are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Mora Porta/Ji and Kanno before him or her, to modify the method of Mora Porta/Ji to include the QLC blocks of Kanno because it will enhance data access.
The motivation for doing so would be [“ reducing the size of a buffer required to be provided in the SSD has been considered necessary” (Column 1, lines 28-30 by Kanno)].
Therefore, it would have been obvious to combine Mora Porta/Ji and Kanno to obtain the invention as specified in the instant claim.
As per dependent claim 6, Kanno discloses wherein each lower-level cell block is a triple-level cell (TLC) block [(Column 31, lines 55-67 and Column 32, lines 1-20) where the controller 4 copies the write data already written to one first storage region (QLC block) managed as the first zone from the one first storage region (QLC block) to the SLC buffer 201 and the like, and thereby sets this one first storage region (QLC block) to the state in which the valid data is not stored. After the total of the data size of the already written write data (i.e., the data size of the copied write data), the data size of remaining write data un-transferred to the internal buffer 161, of the plurality of write data associated with the received first write commands each specifying the first zone, and the data size of the subsequent write data associated with the plurality of subsequent first write commands specifying the first zone, reaches the capacity of the first zone, the controller 4 transfers the remaining write data and the subsequent write data from the write buffer 51 of the host 2 to the internal buffer 161. Then, the controller 4 may open this first storage region (QLC block), write the written write data copied to the SLC buffer 201 and the like, the remaining write data transferred to the internal buffer 161, and the subsequent write data to this first storage region, and thereby set this first storage region to the state in which the whole first storage region is filled with the data to correspond to the claimed limitation].
Claim 10 is rejected under 35 U.S.C. 103(a) as being disclosed by Mora Porta in view of Ji, as applied to claim 1, and further in view of Gong et al. (US PGPUB 2018/0173457 hereinafter referred to as Gong).
As per dependent claim 10, Mora Porta/Ji discloses the system according to claim 1.
Mora Porta/Ji does not appear to explicitly disclose wherein the causing of the data to be transferred from the individual higher-level cell block to one or more lower-level cell blocks of the memory device comprises: releasing the individual higher-level cell block for reuse after data has been copied from the individual higher-level cell block to the one or more lower-level cell blocks
However, Gong discloses wherein the causing of the data to be transferred from the individual higher-level cell block to one or more lower-level cell blocks of the memory device comprises: releasing the individual higher-level cell block for reuse after data has been copied from the individual higher-level cell block to the one or more lower-level cell blocks [(Paragraph 0032) where the temporary buffer(s) 211 and/or 212 can be allocated in advance. In some other embodiments, the temporary buffer(s) 211 and/or 212 can be allocated temporarily for data to be updated, and released after the data is copied to the working buffer(s) 201 and/or 202 to correspond to the claimed limitation].
Mora Porta/Ji and Gong are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Mora Porta/Ji and Gong before him or her, to modify the method of Mora Porta/Ji to include the releasing of the block after the copying blocks of Gong because it will enhance data access.
The motivation for doing so would be [“ensuring data consistency” (Paragraph by Gong)].
Therefore, it would have been obvious to combine Mora Porta/Ji and Gong to obtain the invention as specified in the instant claim.
Claim 13 is rejected under 35 U.S.C. 103(a) as being disclosed by Mora Porta in view of Ji, as applied to claim 1, and further in view of Tuers et al. (US PGPUB 2015/0154112 hereinafter referred to as Tuers).
As per dependent claim 13, Mora Porta/Ji discloses the system according to claim 1.
Mora Porta/Ji does not appear to explicitly disclose determining available data storage capacity of the memory device; and transferring data back from the one or more lower-level cell blocks to one or more higher-level cell blocks based on the available data storage capacity.
However, Tuers discloses determining available data storage capacity of the memory device; and transferring data back from the one or more lower-level cell blocks to one or more higher-level cell blocks based on the available data storage capacity [(Paragraph 0085) where the fold operation may relocate data that has been temporarily cached at the SLC portion 112. The fold operation may be initiated by the controller 134 based on an available storage space of the SLC portion 112. As an illustrative example, if the available storage space at the SLC portion 112 fails to satisfy a threshold, the controller 134 may initiate the fold operation to relocate data from the SLC portion 112 to the MLC portion 124 to increase an amount of available storage space at the SLC portion 112 to correspond to the claimed limitation].
Mora Porta/Ji and Tuers are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Mora Porta/Ji and Tuers before him or her, to modify the method of Mora Porta/Ji to include the transferring data of Tuers because it will enhance data access.
The motivation for doing so would be [“performance of the data storage device 102 is improved” (Paragraph 0089 by Tuers)].
Therefore, it would have been obvious to combine Mora Porta/Ji and Tuers to obtain the invention as specified in the instant claim.
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 2, 4, 7, 16, 18 and 19 are objected to but would be allowable if rewritten in an independent form and address all 112 rejections.
The reasons for allowance of claims 2 and 16 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the causing of the data to be transferred from the individual higher-level cell block to the one or more lower-level cell blocks of the memory device comprises: performing a folding operation on the individual higher-level cell block to cause data to be transferred from the individual higher-level cell block to the one or more lower-level cell blocks”.
The reasons for allowance of claim 4 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the individual higher-level cell block is part of a set of marked higher-level cell blocks that are marked as candidates for higher- level cell-to-lower-level cell block data transfer, and wherein the operations comprise: performing a folding operation on the set of marked higher-level cell blocks, the folding operation causing data of each select higher-level cell block in the set of marked higher-level cell blocks to be transferred to a set of select lower-level cell blocks of the memory device”.
The reason for allowance of claims 7 and 18 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the threshold value is a first threshold value, and wherein the operations comprise: in response to determining that the individual periodic read count is not greater than the first threshold value: determining whether the individual periodic read count is less than or equal to the first threshold value and the individual periodic read count is greater than a second threshold value; and in response to determining that the individual periodic read count is less than or equal to the first threshold value and that the individual periodic read count greater than a second threshold value: determining whether the individual higher-level cell block satisfies at least one trigger condition for transferring the individual higher-level cell block to the one or more lower-level cell blocks; and in response to determining that the individual higher-level cell block satisfies the at least one trigger condition, causing data to be transferred from the individual higher-level cell block to one or more lower-level cell blocks of the memory device”.
The reasons for allowance of claim 19 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the threshold value is a first threshold value, and wherein the operations comprise: in response to determining that the individual periodic read count is not greater than the first threshold value: determining whether the individual periodic read count is less than or equal to the first threshold value and the individual periodic read count is greater than a second threshold value; and in response to determining that the individual periodic read count is less than or equal to the first threshold value and that the individual periodic read count greater than a second threshold value: determining whether the individual higher-level cell block satisfies at least one trigger condition for transferring the individual higher-level cell block to the one or more lower-level cell blocks;and in response to determining that the individual higher-level cell block satisfies the at least one trigger condition, causing data to be transferred from the individual higher-level cell block to one or more lower-level cell blocks of the memory device”.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al., US PGPUB 2021/0124693– teaches MEMORY DEVICE, METHOD OF OPERATING MEMORY DEVICE, AND COMPUTER SYSTEM INCLUDING MEMORY DEVICE.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED GEBRIL whose telephone number is (571)270-1857. The examiner can normally be reached on Monday-Friday, 8:00am-5:00pm.ALT. Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
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