DETAILED ACTION
This action is responsive to the communication filed on 6/26/2026. Claims 1-4, 6-11, 13-18, and 20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 5-6, and 18 of U.S. Patent No. 12293099 in view of Kim et al. (US 20160124641 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the commonly owned patent disclose/obviate the claims on the instant application.
Note that (MPEP 804.0 (I.B.1)) states: A complete response to a nonstatutory double patenting (NDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional.
As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner. See MPEP § 804.02, subsection VI, for filing terminal disclaimers required to overcome nonstatutory double patenting rejections in applications filed on or after June 8, 1995.
Instant application 19085889
U.S. Patent #12293099 (corresponding to Application # 18098439)
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device configured to perform operations, comprising:
initializing a timer at initialization of a block family;
storing a value of the timer before powering down the system while the block family is open; and
upon the system powering up:
determining a value of a data state metric associated with memory cells of the block family;
estimating a time after program value of the memory cells based on the value of the data state metric;
incrementing the value of the timer based on the time after program value; closing the block family based on the incremented value of the timer, and responsive to closing the block family, associating the block family with a threshold voltage offset bin for performing read operations.
2. The system of claim 1, wherein the timer is associated with a system clock, and wherein the operations further comprise:
initializing the block family associated with the memory device; and
associating pages of the memory device, as the pages are programmed, with the block family while the block family is open, wherein the memory cells are associated with a page of the pages.
3. The system of claim 1, wherein the data state metric reflects one of a lower tail location or an upper tail location of a voltage distribution of the memory cells.
6. The system of claim 1, wherein the storing of the value is in non-volatile memory of the memory device.
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device configured to perform operations, comprising:
initializing a block family associated with the memory device;
initializing a timer at initialization of the block family;
associating pages of the memory device, as the pages are programmed, with the block family while the block family is open;
storing, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is open;
detecting a power on of the system;
measuring a data state metric associated with memory cells of the pages, wherein the data state metric reflects one of a lower tail location or an upper tail location of a voltage distribution;
estimating a time after program value of the pages based on comparing a level of the data state metric to a temporal voltage shift function;
incrementing the value of the timer, restored from the non-volatile memory, based on the time after program value; and
closing the block family based on the incremented value of the timer.
2. The system of claim 1, wherein the timer is associated with a system clock.
5. The system of claim 1, wherein the operations further comprise, responsive to closing the block family, associating the block family with a first threshold voltage offset bin.
4. The system of claim 1, wherein the data state metric reflects one of a median of a level seven (L7) distribution, a valley location of a level six (L6) distribution, or a valley location of a level seven (L7) distribution.
18. The system of claim 1, wherein the data state metric further reflects one of a median of a level seven (L7) distribution, a valley location of a level six (L6) distribution, or a valley location of a level seven (L7) distribution.
7. The system of claim 6, wherein the operations further comprise:
tracking, using a circuit-level clock, a time period the memory device is powered off;
detecting the power on of the system; and
updating the value of the timer, restored from the non-volatile memory, based on the time period.
6. The system of claim 1, wherein the operations further comprise:
tracking, using a circuit-level clock, a second time period the memory device is powered off;
detecting the power on of the system; and
updating the value of the timer, restored from the non-volatile memory, based on the second time period.
8. A method comprising:
initializing, by a processing device operatively coupled to a memory device of a system, a timer at initialization of a block family associated with the memory device;
storing a value of the timer before powering down the system while the block family is open; detecting the system powering up; and
upon the system powering up, the method further comprising:
determining, by the processing device, a value of a data state metric associated with memory cells of the block family;
estimating a time after program value of the memory cells based on the value of the data state metric;
incrementing the value of the timer based on the time after program value; closing, by the processing device, the block family based on the incremented value of the timer; and responsive to closing the block family, associating the block family with a threshold voltage offset bin for performing read operations.
9. The method of claim 8, wherein the timer is associated with a system clock, and wherein the method further comprises:
initializing the block family associated with the memory device; and
associating pages of the memory device, as the pages are programmed, with the block family while the block family is open, wherein the memory cells are associated with a page of the pages.
10. The method of claim 8, wherein the data state metric reflects one of a lower tail location or an upper tail location of a voltage distribution of the memory cells.
13. The method of claim 8, wherein the storing of the value is in non-volatile memory of the memory device.
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device configured to perform operations, comprising:
initializing a block family associated with the memory device;
initializing a timer at initialization of the block family;
associating pages of the memory device, as the pages are programmed, with the block family while the block family is open;
storing, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is open;
detecting a power on of the system;
measuring a data state metric associated with memory cells of the pages, wherein the data state metric reflects one of a lower tail location or an upper tail location of a voltage distribution;
estimating a time after program value of the pages based on comparing a level of the data state metric to a temporal voltage shift function;
incrementing the value of the timer, restored from the non-volatile memory, based on the time after program value; and
closing the block family based on the incremented value of the timer.
2. The system of claim 1, wherein the timer is associated with a system clock.
5. The system of claim 1, wherein the operations further comprise, responsive to closing the block family, associating the block family with a first threshold voltage offset bin.
11. The method of claim 8, wherein the data state metric reflects one of a median of a level seven (L7) distribution, a valley location of a level six (L6) distribution, or a valley location of a level seven (L7) distribution.
18. The system of claim 1, wherein the data state metric further reflects one of a median of a level seven (L7) distribution, a valley location of a level six (L6) distribution, or a valley location of a level seven (L7) distribution.
14. The method of claim 13, further comprising:
tracking, using a circuit-level clock, a time period the memory device is powered off;
detecting the power on of the system; and
updating the value of the timer, restored from the non-volatile memory, based on the time period.
6. The system of claim 1, wherein the operations further comprise:
tracking, using a circuit-level clock, a second time period the memory device is powered off;
detecting the power on of the system; and
updating the value of the timer, restored from the non-volatile memory, based on the second time period.
15. A memory sub-system comprising: a memory device; and a processing device, operatively coupled to the memory device, the processing device configured to perform operations, comprising: initializing a timer at initialization of a block family associated with the memory device; storing a value of the timer before powering down the memory sub-system while the block family is open; and upon the memory sub-system powering up, the operations further comprising: determining a value of a data state metric associated with memory cells of the block family; estimating a time after program value of the memory cells based on the value of the data state metric; incrementing the value of the timer based on the time after program value; closing the block family based on the incremented value of the timer and responsive to closing the block family, associating the block family with a threshold voltage offset bin for performing read operations.
16. The memory sub-system of claim 15, wherein the timer is associated with a system clock, and wherein the operations further comprise:
initializing the block family associated with the memory device; and
associating pages of the memory device, as the pages are programmed, with the block family while the block family is open, wherein the memory cells are associated with a page of the pages.
17. The memory sub-system of claim 15, wherein the data state metric reflects one of a lower tail location or an upper tail location of a voltage distribution of the memory cells.
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device configured to perform operations, comprising:
initializing a block family associated with the memory device;
initializing a timer at initialization of the block family;
associating pages of the memory device, as the pages are programmed, with the block family while the block family is open;
storing, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is open;
detecting a power on of the system;
measuring a data state metric associated with memory cells of the pages, wherein the data state metric reflects one of a lower tail location or an upper tail location of a voltage distribution;
estimating a time after program value of the pages based on comparing a level of the data state metric to a temporal voltage shift function;
incrementing the value of the timer, restored from the non-volatile memory, based on the time after program value; and
closing the block family based on the incremented value of the timer.
2. The system of claim 1, wherein the timer is associated with a system clock.
5. The system of claim 1, wherein the operations further comprise, responsive to closing the block family, associating the block family with a first threshold voltage offset bin.
18. The memory sub-system of claim 15, wherein the data state metric reflects one of a median of a level seven (L7) distribution, a valley location of a level six (L6) distribution, or a valley location of a level seven (L7) distribution.
18. The system of claim 1, wherein the data state metric further reflects one of a median of a level seven (L7) distribution, a valley location of a level six (L6) distribution, or a valley location of a level seven (L7) distribution.
20. The memory sub-system of claim 15, wherein the storing of the value is in non-volatile memory of the memory device, and wherein the operations further comprise:
tracking, using a circuit-level clock, a time period the memory device is powered off;
detecting the power on of the system; and
updating the value of the timer, restored from the non-volatile memory, based on the time period.
6. The system of claim 1, wherein the operations further comprise:
tracking, using a circuit-level clock, a second time period the memory device is powered off;
detecting the power on of the system; and
updating the value of the timer, restored from the non-volatile memory, based on the second time period.
Regarding claims 1, 8, and 15, U.S. Patent #12293099 discloses all limitations except the disclosures pertaining to the threshold voltage offset bins being for performing read operations. However, Kim et al. (US 20160124641 A1) teaches associating blocks that are programmed or erased sequentially, simultaneously, or within a critical time period with a same program order stamp (POS) (‘bin’), where a POS is associated with a respective read voltage offset (para. 55, 59-61, 117-125; figs. 1, 10A-10E and associated paragraphs).
U.S. Patent #12293099 and Kim are analogous to the claimed invention involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of U.S. Patent #12293099 and Kim, to modify the disclosures by U.S. Patent #12293099 to include disclosures by Kim since they both teach data storage, wherein Kim is directed towards improved reliability (para. 3, 235). Therefore, it would be applying a known technique (associating blocks programmed or erased within a similar period of time with a stamp associated with a respective read voltage offset) to a known device (system assigning pages programmed in a time period corresponding to a block family with a threshold voltage offset bin for performing read operations) ready for improvement to yield predictable results (system assigning pages programmed in a time period corresponding to a block family with a threshold voltage offset bin associated with a respective read voltage offset in order to provide for improved reliability of the programmed data). MPEP 2143
The double patenting rejection above applies to claims 1-4, 6-11, 13-18, and 20.
Claims 1-2, 6, 8-9, 13, and 15-16 are additionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 4, 7-9, 11, and 14 of U.S. Patent No. 11573720 in view of Kim et al. (US 20160124641 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the commonly owned patent disclose/obviate the claims on the instant application.
Instant application 19044005
U.S. Patent #11573720 (corresponding to Application # 16/947,819)
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device configured to perform operations, comprising:
initializing a timer at initialization of a block family;
storing a value of the timer before powering down the system while the block family is open; and
upon the system powering up:
determining a value of a data state metric associated with memory cells of the block family;
estimating a time after program value of the memory cells based on the value of the data state metric;
incrementing the value of the timer based on the time after program value; closing the block family based on the incremented value of the timer and responsive to closing the block family, associating the block family with a threshold voltage offset bin for performing read operations.
2. The system of claim 1, wherein the timer is associated with a system clock, and wherein the operations further comprise:
initializing the block family associated with the memory device; and
associating pages of the memory device, as the pages are programmed, with the block family while the block family is open, wherein the memory cells are associated with a page of the pages.
6. The system of claim 1, wherein the storing of the value is in non-volatile memory of the memory device.
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device to perform operations, comprising:
initializing a block family associated with the memory device;
initializing a timer at initialization of the block family;
aggregating a plurality of temperature values received from one or more temperature sensors of the memory device over time to determine an aggregate temperature;
responsive to programming a page residing on the memory device, associating the page with the block family;
determining that the timer has reached a first time value in response to the aggregate temperature being greater than a first temperature value;
closing the block family in response to the timer reaching the first time value;
determining that the timer has reached a second time value, which is greater than the first time value, in response to the aggregate temperature being less than or equal to the first temperature value; and
closing the block family in response to the timer reaching the second time value.
2. The system of claim 1, wherein the timer is associated with a system clock, and the operations further comprise, responsive to closing the block family, initializing a new block family.
4. The system of claim 1, wherein the operations further comprise:
storing, in non-volatile memory, a value of the timer before powering down the system while the block family is still open;
detecting a power on of the system;
measuring a data state metric associated with one or more memory cell of the page of the memory device;
comparing a level of the data state metric to a temporal voltage shift function to estimate a time after program value of the page; and
incrementing the value of the timer, restored from the non-volatile memory, based on the time after program value.
7. The system of claim 1, wherein the operations further comprise, responsive to closing the block family, associating the block family with a first threshold voltage offset bin.
8. A method comprising:
initializing, by a processing device operatively coupled to a memory device of a system, a timer at initialization of a block family associated with the memory device;
storing a value of the timer before powering down the system while the block family is open; detecting the system powering up;and
upon the system powering up, the method further comprising:
determining, by the processing device, a value of a data state metric associated with memory cells of the block family;
estimating a time after program value of the memory cells based on the value of the data state metric;
incrementing the value of the timer based on the time after program value; closing, by the processing device, the block family based on the incremented value of the timer; and responsive to closing the block family, associating the block family with a threshold voltage offset bin for performing read operations.
9. The method of claim 8, wherein the timer is associated with a system clock, and wherein the method further comprises:
initializing the block family associated with the memory device; and
associating pages of the memory device, as the pages are programmed, with the block family while the block family is open, wherein the memory cells are associated with a page of the pages.
13. The method of claim 8, wherein the storing of the value is in non-volatile memory of the memory device.
8. A method comprising:
initializing, by a processing device, a block family associated with a memory device;
initializing a timer at initialization of the block family;
aggregating a plurality of temperature values received from one or more temperature sensors of the memory device over time to determine an aggregate temperature;
responsive to programming a page residing on the memory device, associating the page with the block family;
determining that the timer has reached a first time value in response to the aggregate temperature being greater than a first temperature value;
closing, by the processing device, the block family in response to the timer reaching the first time value;
determining that the timer has reached a second time value, which is greater than the first time value, in response to the aggregate temperature being less than or equal to the first temperature value; and
closing, by the processing device, the block family in response to the timer reaching the second time value.
9. The method of claim 8, wherein the timer is associated with a system clock, the method further comprising, responsive to closing the block family, initializing a new block family.
11. The method of claim 8, further comprising:
storing, in non-volatile memory, a value of the timer before powering down the memory device while the block family is still open;
detecting a power on of the memory device;
measuring a data state metric associated with one or more memory cell of the page of the memory device;
comparing a level of the data state metric to a temporal voltage shift function to estimate a time after program value of the page; and
incrementing the value of the timer, restored from the non-volatile memory, based on the time after program value.
14. The method of claim 8, further comprising, responsive to closing the block family, associating the block family with a first threshold voltage offset bin.
15. A memory sub-system comprising: a memory device; and a processing device, operatively coupled to the memory device, the processing device configured to perform operations, comprising: initializing a timer at initialization of a block family associated with the memory device; storing a value of the timer before powering down the memory sub-system while the block family is open; and upon the memory sub-system powering up, the operations further comprising: determining a value of a data state metric associated with memory cells of the block family; estimating a time after program value of the memory cells based on the value of the data state metric; incrementing the value of the timer based on the time after program value; closing the block family based on the incremented value of the timer and responsive to closing the block family, associating the block family with a threshold voltage offset bin for performing read operations.
16. The memory sub-system of claim 15, wherein the timer is associated with a system clock, and wherein the operations further comprise:
initializing the block family associated with the memory device; and
associating pages of the memory device, as the pages are programmed, with the block family while the block family is open, wherein the memory cells are associated with a page of the pages.
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device to perform operations, comprising:
initializing a block family associated with the memory device;
initializing a timer at initialization of the block family;
aggregating a plurality of temperature values received from one or more temperature sensors of the memory device over time to determine an aggregate temperature;
responsive to programming a page residing on the memory device, associating the page with the block family;
determining that the timer has reached a first time value in response to the aggregate temperature being greater than a first temperature value;
closing the block family in response to the timer reaching the first time value;
determining that the timer has reached a second time value, which is greater than the first time value, in response to the aggregate temperature being less than or equal to the first temperature value; and
closing the block family in response to the timer reaching the second time value.
2. The system of claim 1, wherein the timer is associated with a system clock, and the operations further comprise, responsive to closing the block family, initializing a new block family.
4. The system of claim 1, wherein the operations further comprise:
storing, in non-volatile memory, a value of the timer before powering down the system while the block family is still open;
detecting a power on of the system;
measuring a data state metric associated with one or more memory cell of the page of the memory device;
comparing a level of the data state metric to a temporal voltage shift function to estimate a time after program value of the page; and
incrementing the value of the timer, restored from the non-volatile memory, based on the time after program value.
7. The system of claim 1, wherein the operations further comprise, responsive to closing the block family, associating the block family with a first threshold voltage offset bin.
Regarding claims 1, 8, and 15, U.S. Patent #11573720 discloses all limitations except the disclosures pertaining to the threshold voltage offset bins being for performing read operations. However, Kim et al. (US 20160124641 A1) teaches associating blocks that are programmed or erased sequentially, simultaneously, or within a critical time period with a same program order stamp (POS) (‘bin’), where a POS is associated with a respective read voltage offset (para. 55, 59-61, 117-125; figs. 1, 10A-10E and associated paragraphs).
U.S. Patent #11573720 and Kim are analogous to the claimed invention involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of U.S. Patent #11573720 and Kim, to modify the disclosures by U.S. Patent #11573720 to include disclosures by Kim since they both teach data storage, wherein Kim is directed towards improved reliability (para. 3, 235). Therefore, it would be applying a known technique (associating blocks programmed or erased within a similar period of time with a stamp associated with a respective read voltage offset) to a known device (system assigning pages programmed in a time period corresponding to a block family with a threshold voltage offset bin for performing read operations) ready for improvement to yield predictable results (system assigning pages programmed in a time period corresponding to a block family with a threshold voltage offset bin associated with a respective read voltage offset in order to provide for improved reliability of the programmed data). MPEP 2143
The double patenting rejection above applies to claims 1-2, 6, 8-9, 13, 15 and 16.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6, 8-9, 13, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Belgal et al. (US 20130007344 A1) in view of Ronen (US 20050243626 A1) in view of Kim et al. (US 20200356438 A1) in view of Zeng et al. (US 20170345489 A1) in view of Kim et al. (US 20160124641 A1; Kim 2).
As per claim 1,
1. A system comprising: a memory device; and a processing device, operatively coupled to the memory device, the processing device configured to perform operations, comprising: [Belgal teaches a system comprising non-volatile memory and a controller comprising a processor (para. 21, lines 1-10; fig 1 and associated paragraphs)] initializing a timer at initialization of a block family; [Belgal teaches tracking elapsed time, since programming, of respective data locations in a memory partition, where the elapsed time may also include the accumulated time durations between power up to power down events (para. 14, lines 1 – para. 15, line 16; para. 26-31; para. 37, lines 1-12; para. 42-46; also see fig. 1, 4 and associated paragraphs), where Belgal teaches that the elapsed times for each location may be compared to a reference time to determine whether the data in the corresponding location should be relocated (refreshed) and the elapsed time reset (para. 29, line 1- para. 32, line 10; fig. 1 and associated paragraphs), wherein first writing new data into a partition and initiating tracking of the elapsed time may correspond to initializing a block family (location of each data in the partition) and tracking of the elapsed time with writing the data may correspond to initializing a timer] storing a value of the timer before powering down the system while the block family is open; and upon the system powering up: [Belgal teaches storing the elapsed times for data locations prior to powering down and, upon powering up, loading stored timestamps and determining elapsed time (para 48, lines 1-18; para. 41, lines 1- para. 43, line 14; fig. 4 and associated paragraphs), wherein the locations in the partition containing written data may comprise block family, wherein the locations in the partition not having been refreshed may correspond to the block family being open]
Belgal does not explicitly disclose, but Ronen discloses:
closing the block family based on the incremented value of the timer; and [Where Belgal discloses writing data to locations of a memory partition and refreshing the data based on the timer as shown above, Belgal’s disclosure is directed to refreshing each location based on the respective timers. While Belgal’s disclosure does not explicitly guarantee refraining from refreshing the locations in the partition while data is being written to other locations in the partition (keeping the block family open) and does not disclose refreshing the data in the multiple locations together as a unit (closing the block family) based on a timer, Ronen discloses flash memory comprising memory cells pages and blocks (para. 29) and refreshing data from cells being erased into a new set of cells (para. 28) based on a timestamp stored with the data being programmed (para. 30); Ronen discloses that the number of cells of data that can be refreshed in a single pass can be flexible and the cells comprising units larger than a page being refreshed together may have a single timestamp stored in the first page (para. 29-31), where it would have been obvious for one of ordinary skill in the arts to have combined the disclosures by Belgal providing for refreshing each location of a memory partition based on respective elapsed times with Ronen’s disclosure directed towards refreshing memory cells in flexible quantities based on a timestamp associated with the memory cells in order to provide for a combination where the data locations in the memory partition may be refreshed together based on an elapsed time referenced with the first page of the partition in order to provide for more predictable use of system resources for refreshing memory segments]
Belgal and Ronen are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal and Ronen, to modify the disclosures by Belgal to include disclosures by Ronen since they both teach data storage and memory access, wherein Ronen is directed towards improved retention time (para. 7). Therefore, it would be applying a known technique (refreshing memory cells in flexible quantities based on a timestamp stored in a first page) to a known device (memory device refreshing each location of a memory partition based on respective elapsed times, wherein the elapsed time may be stored prior to powering down and retrieved upon powering on) ready for improvement to yield predictable results (memory device refreshing data locations in the memory partition together based on an elapsed time referenced with the first page of the partition, wherein the elapsed time may be stored prior to powering down and retrieved upon powering on, in order to provide for more predictable use of system resources for refreshing memory segments). MPEP 2143
Belgal in view of Ronen does not explicitly disclose, but Kim discloses:
incrementing the value of the timer based on the time after program value; [Belgal in view of Ronen as shown above teaches using elapsed time including the accumulated durations of power up to power down (see the rejection above); Kim teaches reclaiming a memory block in a storage device based on time elapsed since a block was programmed reaching a reference time, where, if the storage device was powered off prior to reaching the reference time, Kim teaches adding a power-off period to the elapsed time (incrementing) for calculating whether sum exceeds the reference time (para. 33, lines 1-29)]
Belgal, Ronen, and Kim are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal in view of Ronen and Kim, to modify the disclosures by Belgal in view of Ronen to include disclosures by Kim since they both teach data storage and memory access, wherein Kim is directed towards improved reliability of storage devices (para. 3). Therefore, it would be applying a known technique (tracking time since programming data including powered-off time for determining whether a block should be reclaimed) to a known device (memory device tracking time since programming data in a partition without including powered-off time for determining whether the partition should be refreshed) ready for improvement to yield predictable results (memory device tracking time since programming data including powered-off time for determining whether a partition should be refreshed in order to provide for improved data integrity from accounting for data deterioration associated with the powered off duration). MPEP 2143
Belgal in view of Ronen in view of Kim does not explicitly disclose, but Zeng discloses:
determining a value of a data state metric associated with memory cells of the block family; estimating a time after program value of the memory cells based on the value of the data state metric; [Where Belgal in view of Ronen in view of Kim as shown above teaches accounting for powered off period in determining time elapsed since programming (see above); it does not explicitly disclose, but Zeng discloses using blocks’ state parameters to determine read voltage shift and estimating power-off period according to the read voltage shift (para. 71-72); it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Belgal in view of Ronen in view of Kim, directed towards determining time since programming including powered off periods, and disclosures by Zeng, directed towards using state parameters in determining a power-off period, to provide for a combination where time since programming may be determined using state parameters to account for powered-off periods in order to provide for additional (i.e. in lieu of a clock) means for accounting for time passage associated with power loss.]
Belgal, Ronen, Kim, and Zeng are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal in view of Ronen in view of Kim and Zeng, to modify the disclosures by Belgal in view of Ronen in view of Kim to include disclosures by Zeng since they both teach data storage and memory access, wherein Zeng is directed towards improved operational speed of storage devices (para. 26). Therefore, it would be applying a known technique (tracking a powered-off duration of a device by using state parameters) to a known device (memory device tracking time since programming data including powered-off time for determining whether a partition should be refreshed) ready for improvement to yield predictable results (memory device tracking time since programming data, including powered-off time determined through data state parameters, for determining whether a partition should be refreshed in order to reduce reliance on host devices or other power sources for tracking the passage of time). MPEP 2143
Belgal in view of Ronen in view of Kim in view of Zeng does not explicitly disclose, but Kim 2 discloses:
responsive to closing the block family, associating the block family with a threshold voltage offset bin for performing read operations. [Belgal in view of Ronen in view of Kim in view of Zeng as shown above teaches refreshing a partition based on a timer as shown above and also teaches erasing the data in the refreshed (closed) partition (Belgal: para. 17, 30; Ronen: para. 28); Kim 2 teaches associating blocks/pages that are programmed or erased sequentially, simultaneously, or within a critical time period with a same program order stamp (POS) (‘bin’), where a POS is associated with a respective read voltage offset (para. 55, 59-61, 117-125; figs. 1, 10A-10E and associated paragraphs)]
Belgal, Ronen, Kim, Zeng, and Kim 2 are analogous to the claimed invention involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal in view of Ronen in view of Kim in view of Zeng and Kim 2, to modify the disclosures by Belgal in view of Ronen in view of Kim in view of Zeng to include disclosures by Kim 2 since they both teach data storage, wherein Kim 2 is directed towards improved reliability (para. 3, 235). Therefore, it would be applying a known technique (associating blocks/pages erased within a similar period of time with a stamp associated with a respective read voltage offset) to a known device (memory device erasing blocks of a partition upon refreshing the partition) ready for improvement to yield predictable results (memory device erasing blocks of a partition upon refreshing the partition, where the erased blocks are associated with a stamp associated with a read voltage offset to provide for read voltage usable for operations such as erase verification). MPEP 2143
As per claim 2, Belgal in view of Ronen in view of Kim in view of Zeng in view of Kim 2 teaches claim 1 as shown above and further teaches:
2. The system of claim 1, wherein the timer is associated with a system clock, and [Belgal teaches a system clock for updating elapsed times (para. 37, lines 1-12)] wherein the operations further comprise: initializing the block family associated with the memory device; and associating pages of the memory device, as the pages are programmed, with the block family while the block family is open, wherein the memory cells are associated with a page of the pages. [Belgal in view of Ronen in view of Kim in view of Zeng in view of Kim 2 as shown above teaches refreshing locations in the partition together according to a timer, where the refreshing may be performed in units larger than a page (see claim 1 above; Ronen: para. 28-31), where pages of the partition being written to prior to refreshing of the partition may correspond to associating the pages with the block family while the block family is open]
Belgal and Ronen are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal and Ronen, to modify the disclosures by Belgal to include disclosures by Ronen since they both teach data storage and memory access, wherein Ronen is directed towards improved retention time (para. 7). Therefore, it would be applying a known technique (refreshing memory cells in flexible quantities based on a timestamp stored in a first page) to a known device (memory device refreshing each location of a memory partition based on respective elapsed times, wherein the elapsed time may be stored prior to powering down and retrieved upon powering on) ready for improvement to yield predictable results (memory device refreshing data locations in the memory partition together based on an elapsed time referenced with the first page of the partition, wherein the elapsed time may be stored prior to powering down and retrieved upon powering on, in order to provide for more predictable use of system resources for refreshing memory segments). MPEP 2143
As per claim 6, Belgal in view of Ronen in view of Kim in view of Zeng in view of Kim 2 teaches claim 1 as shown above and further teaches:
6. The system of claim 1, wherein the storing of the value is in non-volatile memory of the memory device. [Belgal teaches storing elapsed times for data locations in a partition of a non-volatile memory (para. 48, 21; figs. 1, 4 and associated paragraphs)]
As per claim 8,
A method comprising: initializing, by a processing device operatively coupled to a memory device of a system, a timer at initialization of a block family associated with the memory device; [Belgal teaches a system comprising non-volatile memory and a controller comprising a processor (para. 21, lines 1-10; fig 1 and associated paragraphs); Belgal teaches tracking elapsed time, since programming, of respective data locations in a memory partition, where the elapsed time may also include the accumulated time durations between power up to power down events (para. 14, lines 1 – para. 15, line 16; para. 26-31; para. 37, lines 1-12; para. 42-46; also see fig. 1, 4 and associated paragraphs), where Belgal teaches that the elapsed times for each location may be compared to a reference time to determine whether the data in the corresponding location should be relocated (refreshed) and the elapsed time reset (para. 29, line 1- para. 32, line 10; fig. 1 and associated paragraphs), wherein first writing new data into a partition and initiating tracking of the elapsed time may correspond to initializing a block family (location of each data in the partition) and tracking of the elapsed time with writing the data may correspond to initializing a timer] storing a value of the timer before powering down the system while the block family is open; detecting the system powering up; and upon the system powering up, the method further comprising: [Belgal teaches storing the elapsed times for data locations prior to powering down and, upon powering up, loading stored timestamps and determining elapsed time (para 48, lines 1-18; para. 41, lines 1- para. 43, line 14; fig. 4 and associated paragraphs), wherein the locations in the partition containing written data may comprise block family, wherein the locations in the partition not having been refreshed may correspond to the block family being open]
Belgal does not explicitly disclose, but Ronen discloses:
closing, by the processing device, the block family based on the incremented value of the timer; and [Where Belgal discloses writing data to locations of a memory partition and refreshing the data based on the timer as shown above, Belgal’s disclosure is directed to refreshing each location based on the respective timers. While Belgal’s disclosure does not explicitly guarantee refraining from refreshing the locations in the partition while data is being written to other locations in the partition (keeping the block family open) and does not disclose refreshing the data in the multiple locations together as a unit (closing the block family) based on a timer, Ronen discloses flash memory comprising memory cells pages and blocks (para. 29) and refreshing data from cells being erased into a new set of cells (para. 28) based on a timestamp stored with the data being programmed (para. 30); Ronen discloses that the number of cells of data that can be refreshed in a single pass can be flexible and the cells comprising units larger than a page being refreshed together may have a single timestamp stored in the first page (para. 29-31), where it would have been obvious for one of ordinary skill in the arts to have combined the disclosures by Belgal providing for refreshing each location of a memory partition based on respective elapsed times with Ronen’s disclosure directed towards refreshing memory cells in flexible quantities based on a timestamp associated with the memory cells in order to provide for a combination where the data locations in the memory partition may be refreshed together based on an elapsed time referenced with the first page of the partition in order to provide for more predictable use of system resources for refreshing memory segments]
Belgal and Ronen are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal and Ronen, to modify the disclosures by Belgal to include disclosures by Ronen since they both teach data storage and memory access, wherein Ronen is directed towards improved retention time (para. 7). Therefore, it would be applying a known technique (refreshing memory cells in flexible quantities based on a timestamp stored in a first page) to a known device (memory device refreshing each location of a memory partition based on respective elapsed times, wherein the elapsed time may be stored prior to powering down and retrieved upon powering on) ready for improvement to yield predictable results (memory device refreshing data locations in the memory partition together based on an elapsed time referenced with the first page of the partition, wherein the elapsed time may be stored prior to powering down and retrieved upon powering on, in order to provide for more predictable use of system resources for refreshing memory segments). MPEP 2143
Belgal in view of Ronen does not explicitly disclose, but Kim discloses:
incrementing the value of the timer based on the time after program value; [Belgal in view of Ronen as shown above teaches using elapsed time including the accumulated durations of power up to power down (see the rejection above); Kim teaches reclaiming a memory block in a storage device based on time elapsed since a block was programmed reaching a reference time, where, if the storage device was powered off prior to reaching the reference time, Kim teaches adding a power-off period to the elapsed time (incrementing) for calculating whether sum exceeds the reference time (para. 33, lines 1-29)]
Belgal, Ronen, and Kim are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal in view of Ronen and Kim, to modify the disclosures by Belgal in view of Ronen to include disclosures by Kim since they both teach data storage and memory access, wherein Kim is directed towards improved reliability of storage devices (para. 3). Therefore, it would be applying a known technique (tracking time since programming data including powered-off time for determining whether a block should be reclaimed) to a known device (memory device tracking time since programming data in a partition without including powered-off time for determining whether the partition should be refreshed) ready for improvement to yield predictable results (memory device tracking time since programming data including powered-off time for determining whether a partition should be refreshed in order to provide for improved data integrity from accounting for data deterioration associated with the powered off duration). MPEP 2143
Belgal in view of Ronen in view of Kim does not explicitly disclose, but Zeng discloses:
determining, by the processing device, a value of a data state metric associated with memory cells of the block family; estimating a time after program value of the memory cells based on the value of the data state metric; [Where Belgal in view of Ronen in view of Kim as shown above teaches accounting for powered off period in determining time elapsed since programming (see above); it does not explicitly disclose, but Zeng discloses using blocks’ state parameters to determine read voltage shift and estimating power-off period according to the read voltage shift (para. 71-72); it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Belgal in view of Ronen in view of Kim, directed towards determining time since programming including powered off periods, and disclosures by Zeng, directed towards using state parameters in determining a power-off period, to provide for a combination where time since programming may be determined using state parameters to account for powered-off periods in order to provide for additional (i.e. in lieu of a clock) means for accounting for time passage associated with power loss.]
Belgal, Ronen, Kim, and Zeng are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal in view of Ronen in view of Kim and Zeng, to modify the disclosures by Belgal in view of Ronen in view of Kim to include disclosures by Zeng since they both teach data storage and memory access, wherein Zeng is directed towards improved operational speed of storage devices (para. 26). Therefore, it would be applying a known technique (tracking a powered-off duration of a device by using state parameters) to a known device (memory device tracking time since programming data including powered-off time for determining whether a partition should be refreshed) ready for improvement to yield predictable results (memory device tracking time since programming data, including powered-off time determined through data state parameters, for determining whether a partition should be refreshed in order to reduce reliance on host devices or other power sources for tracking the passage of time). MPEP 2143
Belgal in view of Ronen in view of Kim in view of Zeng does not explicitly disclose, but Kim 2 discloses:
responsive to closing the block family, associating the block family with a threshold voltage offset bin for performing read operations. [Belgal in view of Ronen in view of Kim in view of Zeng as shown above teaches refreshing a partition based on a timer as shown above and also teaches erasing the data in the refreshed (closed) partition (Belgal: para. 17, 30; Ronen: para. 28); Kim 2 teaches associating blocks/pages that are programmed or erased sequentially, simultaneously, or within a critical time period with a same program order stamp (POS) (‘bin’), where a POS is associated with a respective read voltage offset (para. 55, 59-61, 117-125; figs. 1, 10A-10E and associated paragraphs)]
Belgal, Ronen, Kim, Zeng, and Kim 2 are analogous to the claimed invention involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal in view of Ronen in view of Kim in view of Zeng and Kim 2, to modify the disclosures by Belgal in view of Ronen in view of Kim in view of Zeng to include disclosures by Kim 2 since they both teach data storage, wherein Kim 2 is directed towards improved reliability (para. 3, 235). Therefore, it would be applying a known technique (associating blocks/pages erased within a similar period of time with a stamp associated with a respective read voltage offset) to a known device (memory device erasing blocks of a partition upon refreshing the partition) ready for improvement to yield predictable results (memory device erasing blocks of a partition upon refreshing the partition, where the erased blocks are associated with a stamp associated with a read voltage offset to provide for read voltage usable for operations such as erase verification). MPEP 2143
Claim 9 is rejected for reasons similar to claim 2 above.
Claim 13 is rejected for reasons similar to claim 6 above.
As per claim 15,
A memory sub-system comprising: a memory device; and a processing device, operatively coupled to the memory device, the processing device configured to perform operations, comprising: [Belgal teaches a system comprising non-volatile memory and a controller comprising a processor (para. 21, lines 1-10; fig 1 and associated paragraphs)] initializing a timer at initialization of a block family associated with the memory device; [Belgal teaches tracking elapsed time, since programming, of respective data locations in a memory partition, where the elapsed time may also include the accumulated time durations between power up to power down events (para. 14, lines 1 – para. 15, line 16; para. 26-31; para. 37, lines 1-12; para. 42-46; also see fig. 1, 4 and associated paragraphs), where Belgal teaches that the elapsed times for each location may be compared to a reference time to determine whether the data in the corresponding location should be relocated (refreshed) and the elapsed time reset (para. 29, line 1- para. 32, line 10; fig. 1 and associated paragraphs), wherein first writing new data into a partition and initiating tracking of the elapsed time may correspond to initializing a block family (location of each data in the partition) and tracking of the elapsed time with writing the data may correspond to initializing a timer] storing a value of the timer before powering down the memory sub-system while the block family is open; and upon the memory sub-system powering up, the operations further comprising: [Belgal teaches storing the elapsed times for data locations prior to powering down and, upon powering up, loading stored timestamps and determining elapsed time (para 48, lines 1-18; para. 41, lines 1- para. 43, line 14; fig. 4 and associated paragraphs), wherein the locations in the partition containing written data may comprise block family, wherein the locations in the partition not having been refreshed may correspond to the block family being open]
Belgal does not explicitly disclose, but Ronen discloses:
closing the block family based on the incremented value of the timer; and [Where Belgal discloses writing data to locations of a memory partition and refreshing the data based on the timer as shown above, Belgal’s disclosure is directed to refreshing each location based on the respective timers. While Belgal’s disclosure does not explicitly guarantee refraining from refreshing the locations in the partition while data is being written to other locations in the partition (keeping the block family open) and does not disclose refreshing the data in the multiple locations together as a unit (closing the block family) based on a timer, Ronen discloses flash memory comprising memory cells pages and blocks (para. 29) and refreshing data from cells being erased into a new set of cells (para. 28) based on a timestamp stored with the data being programmed (para. 30); Ronen discloses that the number of cells of data that can be refreshed in a single pass can be flexible and the cells comprising units larger than a page being refreshed together may have a single timestamp stored in the first page (para. 29-31), where it would have been obvious for one of ordinary skill in the arts to have combined the disclosures by Belgal providing for refreshing each location of a memory partition based on respective elapsed times with Ronen’s disclosure directed towards refreshing memory cells in flexible quantities based on a timestamp associated with the memory cells in order to provide for a combination where the data locations in the memory partition may be refreshed together based on an elapsed time referenced with the first page of the partition in order to provide for more predictable use of system resources for refreshing memory segments]
Belgal and Ronen are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal and Ronen, to modify the disclosures by Belgal to include disclosures by Ronen since they both teach data storage and memory access, wherein Ronen is directed towards improved retention time (para. 7). Therefore, it would be applying a known technique (refreshing memory cells in flexible quantities based on a timestamp stored in a first page) to a known device (memory device refreshing each location of a memory partition based on respective elapsed times, wherein the elapsed time may be stored prior to powering down and retrieved upon powering on) ready for improvement to yield predictable results (memory device refreshing data locations in the memory partition together based on an elapsed time referenced with the first page of the partition, wherein the elapsed time may be stored prior to powering down and retrieved upon powering on, in order to provide for more predictable use of system resources for refreshing memory segments). MPEP 2143
Belgal in view of Ronen does not explicitly disclose, but Kim discloses:
incrementing the value of the timer based on the time after program value; [Belgal in view of Ronen as shown above teaches using elapsed time including the accumulated durations of power up to power down (see the rejection above); Kim teaches reclaiming a memory block in a storage device based on time elapsed since a block was programmed reaching a reference time, where, if the storage device was powered off prior to reaching the reference time, Kim teaches adding a power-off period to the elapsed time (incrementing) for calculating whether sum exceeds the reference time (para. 33, lines 1-29)]
Belgal, Ronen, and Kim are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal in view of Ronen and Kim, to modify the disclosures by Belgal in view of Ronen to include disclosures by Kim since they both teach data storage and memory access, wherein Kim is directed towards improved reliability of storage devices (para. 3). Therefore, it would be applying a known technique (tracking time since programming data including powered-off time for determining whether a block should be reclaimed) to a known device (memory device tracking time since programming data in a partition without including powered-off time for determining whether the partition should be refreshed) ready for improvement to yield predictable results (memory device tracking time since programming data including powered-off time for determining whether a partition should be refreshed in order to provide for improved data integrity from accounting for data deterioration associated with the powered off duration). MPEP 2143
Belgal in view of Ronen in view of Kim does not explicitly disclose, but Zeng discloses:
determining a value of a data state metric associated with memory cells of the block family; estimating a time after program value of the memory cells based on the value of the data state metric; [Where Belgal in view of Ronen in view of Kim as shown above teaches accounting for powered off period in determining time elapsed since programming (see above); it does not explicitly disclose, but Zeng discloses using blocks’ state parameters to determine read voltage shift and estimating power-off period according to the read voltage shift (para. 71-72); it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Belgal in view of Ronen in view of Kim, directed towards determining time since programming including powered off periods, and disclosures by Zeng, directed towards using state parameters in determining a power-off period, to provide for a combination where time since programming may be determined using state parameters to account for powered-off periods in order to provide for additional (i.e. in lieu of a clock) means for accounting for time passage associated with power loss.]
Belgal, Ronen, Kim, and Zeng are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal in view of Ronen in view of Kim and Zeng, to modify the disclosures by Belgal in view of Ronen in view of Kim to include disclosures by Zeng since they both teach data storage and memory access, wherein Zeng is directed towards improved operational speed of storage devices (para. 26). Therefore, it would be applying a known technique (tracking a powered-off duration of a device by using state parameters) to a known device (memory device tracking time since programming data including powered-off time for determining whether a partition should be refreshed) ready for improvement to yield predictable results (memory device tracking time since programming data, including powered-off time determined through data state parameters, for determining whether a partition should be refreshed in order to reduce reliance on host devices or other power sources for tracking the passage of time). MPEP 2143
Belgal in view of Ronen in view of Kim in view of Zeng does not explicitly disclose, but Kim 2 discloses:
responsive to closing the block family, associating the block family with a threshold voltage offset bin for performing read operations. [Belgal in view of Ronen in view of Kim in view of Zeng as shown above teaches refreshing a partition based on a timer as shown above and also teaches erasing the data in the refreshed (closed) partition (Belgal: para. 17, 30; Ronen: para. 28); Kim 2 teaches associating blocks/pages that are programmed or erased sequentially, simultaneously, or within a critical time period with a same program order stamp (POS) (‘bin’), where a POS is associated with a respective read voltage offset (para. 55, 59-61, 117-125; figs. 1, 10A-10E and associated paragraphs)]
Belgal, Ronen, Kim, Zeng, and Kim 2 are analogous to the claimed invention involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Belgal in view of Ronen in view of Kim in view of Zeng and Kim 2, to modify the disclosures by Belgal in view of Ronen in view of Kim in view of Zeng to include disclosures by Kim 2 since they both teach data storage, wherein Kim 2 is directed towards improved reliability (para. 3, 235). Therefore, it would be applying a known technique (associating blocks/pages erased within a similar period of time with a stamp associated with a respective read voltage offset) to a known device (memory device erasing blocks of a partition upon refreshing the partition) ready for improvement to yield predictable results (memory device erasing blocks of a partition upon refreshing the partition, where the erased blocks are associated with a stamp associated with a read voltage offset to provide for read voltage usable for operations such as erase verification). MPEP 2143
Claim 16 is rejected for reasons similar to claim 2 above.
Claims 7, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Belgal et al. (US 20130007344 A1) in view of Ronen (US 20050243626 A1) in view of Kim et al. (US 20200356438 A1) in view of Zeng et al. (US 20170345489 A1) in view of Kim et al. (US 20160124641 A1; Kim 2) in view of Chance et al. (US 20150143156 A1).
As per claim 7, Belgal in view of Ronen in view of Kim in view of Zeng in view of Kim 2 teaches claim 6 as shown and further teaches:
7. The system of claim 6, wherein the operations further comprise: detecting the power on of the system; and updating the value of the timer, restored from the non-volatile memory, based on the time period. [Bengal teaches managing an elapsed time which includes the accumulated power up durations, wherein elapsed time can be stored prior to a power down event (para. 14, lines 1 – para. 15, line 16; para 48, lines 1-18; para. 41, lines 1- para. 43, line 14); Kim teaches managing an elapsed time by incrementing powered down durations to elapsed time upon powering on (para. 33, lines 1-29; see rejection in claim 1 above)]
Belgal in view of Ronen in view of Kim in view of Zeng in view of Kim 2 does not explicitly disclose, but Chance discloses:
tracking, using a circuit-level clock, a time period the memory device is powered off; [Chance teaches a time component for tracking a time value when the system is off, where the time component may be charged while the system is on but tracks time while the system is off without using additional power, and where the time value is used to update the real clock (para. 23-24; para. 33; 36-37; figs 1-3 and associated paragraphs; abstract; see para. 33 providing the time component may be a capacitor interacting with other circuits such as oscillator (para. 29-34; fig. 2 and associated paragraphs))]
Belgal, Ronen, Kim, Zeng, Kim 2, and Chance are analogous to the claimed invention involving means for tracking time.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Belgal in view of Ronen in view of Kim in view of Zeng in view of Kim 2 with Chance’s disclosures directed towards charged clock that does not require external power used to track the passage of time when the system is unpowered. Doing so would allow for avoiding device operations’ degradation caused by a power loss that may render a real time clock inoperable (para. 1-3).
Claim 14 is rejected for reasons similar to claim 7.
As per claim 20, Belgal in view of Ronen in view of Kim in view of Zeng in view of Kim 2 teaches claim 15 as shown and further teaches:
The memory sub-system of claim 15, wherein the storing of the value is in non-volatile memory of the memory device, and [Belgal teaches storing elapsed times for data locations in a partition of a non-volatile memory (para. 48, 21; figs. 1, 4 and associated paragraphs)] wherein the operations further comprise: detecting the power on of the memory sub-system; and updating the value of the timer, restored from the non-volatile memory, based on the time period. [Bengal teaches managing an elapsed time which includes the accumulated power up durations, wherein elapsed time can be stored prior to a power down event (para. 14, lines 1 – para. 15, line 16; para 48, lines 1-18; para. 41, lines 1- para. 43, line 14); Kim teaches managing an elapsed time by incrementing powered down durations to elapsed time upon powering on (para. 33, lines 1-29; see rejection in claim 15 above)]
Belgal in view of Ronen in view of Kim in view of Zeng in view of Kim 2 does not explicitly disclose, but Chance discloses:
tracking, using a circuit-level clock, a time period the memory device is powered off; [Chance teaches a time component for tracking a time value when the system is off, where the time component may be charged while the system is on but tracks time while the system is off without using additional power, and where the time value is used to update the real clock (para. 23-24; para. 33; 36-37; figs 1-3 and associated paragraphs; abstract; see para. 33 providing the time component may be a capacitor interacting with other circuits such as oscillator (para. 29-34; fig. 2 and associated paragraphs))]
Belgal, Ronen, Kim, Zeng, Kim 2, and Chance are analogous to the claimed invention involving means for tracking time.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Belgal in view of Ronen in view of Kim in view of Zeng in view of Kim 2 with Chance’s disclosures directed towards charged clock that does not require external power used to track the passage of time when the system is unpowered. Doing so would allow for avoiding device operations’ degradation caused by a power loss that may render a real time clock inoperable (para. 1-3).
Allowable Subject Matter
Claims 3-4, 10-11, and 17-18 are rejected on the ground of nonstatutory double patenting as shown above and objected for being dependent on a rejected claim. But the claims would be allowable if they were further amended to overcome the nonstatutory double patenting rejections or through a timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d), in addition to being rewritten, in an independent form, to include the limitations of the instant claim(s) and the base independent claim(s) on which they are dependent on.
With respect to claim 3, “… wherein the data state metric reflects one of a lower tail location or an upper tail location of a voltage distribution of the memory cells.” in conjunction with the other limitations of the claim and the base independent claim, are not disclosed by the prior art of record.
The closest prior arts of record are Belgal et al. (US 20130007344 A1), Ronen (US 20050243626 A1), Kim et al. (US 20200356438 A1), Zeng et al. (US 20170345489 A1), Lee (US 20180081551 A1), Chunn et al. (US 20150169398 A1), Fitzpatrick et al. (US 9543025 B2), and Rotem et al. (US 11029744 B2)
Belgal teaches associating locations in a partition with timestamps and elapsed time. Ronen teaches refreshing memory cells based on a referenced timer. Kim teaches accounting for power off duration in measuring elapsed time since programming a block. Zeng teaches determining read voltage shift to determine power off duration. Lee teaches checking a head or tail region of a block to determine whether a program operation was successful at the time of a power-off. Chun teaches determining temperature, time stamp, and P/E cycle counts during power-on and power-off times. Fitzpatrick teaches determining data decay for estimating power off duration. Rotem teaches calculating a total elapsed lifetime duration of a system comprising active and inactive durations.
However, the prior arts of record, neither individually nor in combination, teaches, with respect to initialization of a block family, initializing a timer at the initialization of the block family and storing a value of the timer while the block family is open prior to powering down the system, where, upon powering up, a value of a data state metric reflecting one of a lower tail location or an upper tail location of a voltage distribution of memory cells of the block family is determined and used for estimating a time after program value of the memory cells, where the value of the timer is incremented based on the obtained time after program value, and, based on the incremented value of the timer, the block family is closed.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim and the base independent claim, the claim as a whole.
With respect to claim 4, “… wherein the data state metric reflects one of a median of a level seven (L7) distribution, a valley location of a level six (L6) distribution, or a valley location of a level seven (L7) distribution.” in conjunction with the other limitations of the claim and the base independent claim, are not disclosed by the prior art of record.
The closest prior arts of record are Belgal et al. (US 20130007344 A1), Ronen (US 20050243626 A1), Kim et al. (US 20200356438 A1), Zeng et al. (US 20170345489 A1), Lee (US 20180081551 A1), Chunn et al. (US 20150169398 A1), Fitzpatrick et al. (US 9543025 B2), and Rotem et al. (US 11029744 B2)
Belgal teaches associating locations in a partition with timestamps and elapsed time. Ronen teaches refreshing memory cells based on a referenced timer. Kim teaches accounting for power off duration in measuring elapsed time since programming a block. Zeng teaches determining read voltage shift to determine power off duration. Lee teaches checking a head or tail region of a block to determine whether a program operation was successful at the time of a power-off. Chun teaches determining temperature, time stamp, and P/E cycle counts during power-on and power-off times. Fitzpatrick teaches determining data decay for estimating power off duration. Rotem teaches calculating a total elapsed lifetime duration of a system comprising active and inactive durations.
However, the prior arts of record, neither individually nor in combination, teaches, with respect to initialization of a block family, initializing a timer at the initialization of the block family and storing a value of the timer while the block family is open prior to powering down the system, where, upon powering up, a value of a data state metric reflecting one of a median of a level seven distribution, a valley location of a level six distribution, or a valley location of a level seven distribution associated with the memory cells of the block family is determined and used for estimating a time after program value of the memory cells, where the value of the timer is incremented based on the obtained time after program value, and, based on the incremented value of the timer, the block family is closed.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim and the base independent claim, the claim as a whole.
With respect to claim 10, “… wherein the data state metric reflects one of a lower tail location or an upper tail location of a voltage distribution of the memory cells.” in conjunction with the other limitations of the claim and the base independent claim, are not disclosed by the prior art of record.
The closest prior arts of record are Belgal et al. (US 20130007344 A1), Ronen (US 20050243626 A1), Kim et al. (US 20200356438 A1), Zeng et al. (US 20170345489 A1), Lee (US 20180081551 A1), Chunn et al. (US 20150169398 A1), Fitzpatrick et al. (US 9543025 B2), and Rotem et al. (US 11029744 B2)
Belgal teaches associating locations in a partition with timestamps and elapsed time. Ronen teaches refreshing memory cells based on a referenced timer. Kim teaches accounting for power off duration in measuring elapsed time since programming a block. Zeng teaches determining read voltage shift to determine power off duration. Lee teaches checking a head or tail region of a block to determine whether a program operation was successful at the time of a power-off. Chun teaches determining temperature, time stamp, and P/E cycle counts during power-on and power-off times. Fitzpatrick teaches determining data decay for estimating power off duration. Rotem teaches calculating a total elapsed lifetime duration of a system comprising active and inactive durations.
However, the prior arts of record, neither individually nor in combination, teaches, with respect to initialization of a block family, initializing a timer at the initialization of the block family and storing a value of the timer while the block family is open prior to powering down the system, where, upon powering up, a value of a data state metric reflecting one of a lower tail location or an upper tail location of a voltage distribution of memory cells of the block family is determined and used for estimating a time after program value of the memory cells, where the value of the timer is incremented based on the obtained time after program value, and, based on the incremented value of the timer, the block family is closed.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim and the base independent claim, the claim as a whole.
With respect to claim 11, “… wherein the data state metric reflects one of a median of a level seven (L7) distribution, a valley location of a level six (L6) distribution, or a valley location of a level seven (L7) distribution.” in conjunction with the other limitations of the claim and the base independent claim, are not disclosed by the prior art of record.
The closest prior arts of record are Belgal et al. (US 20130007344 A1), Ronen (US 20050243626 A1), Kim et al. (US 20200356438 A1), Zeng et al. (US 20170345489 A1), Lee (US 20180081551 A1), Chunn et al. (US 20150169398 A1), Fitzpatrick et al. (US 9543025 B2), and Rotem et al. (US 11029744 B2)
Belgal teaches associating locations in a partition with timestamps and elapsed time. Ronen teaches refreshing memory cells based on a referenced timer. Kim teaches accounting for power off duration in measuring elapsed time since programming a block. Zeng teaches determining read voltage shift to determine power off duration. Lee teaches checking a head or tail region of a block to determine whether a program operation was successful at the time of a power-off. Chun teaches determining temperature, time stamp, and P/E cycle counts during power-on and power-off times. Fitzpatrick teaches determining data decay for estimating power off duration. Rotem teaches calculating a total elapsed lifetime duration of a system comprising active and inactive durations.
However, the prior arts of record, neither individually nor in combination, teaches, with respect to initialization of a block family, initializing a timer at the initialization of the block family and storing a value of the timer while the block family is open prior to powering down the system, where, upon powering up, a value of a data state metric reflecting one of a median of a level seven distribution, a valley location of a level six distribution, or a valley location of a level seven distribution associated with the memory cells of the block family is determined and used for estimating a time after program value of the memory cells, where the value of the timer is incremented based on the obtained time after program value, and, based on the incremented value of the timer, the block family is closed.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim and the base independent claim, the claim as a whole.
With respect to claim 17, “… wherein the data state metric reflects one of a lower tail location or an upper tail location of a voltage distribution of the memory cells.” in conjunction with the other limitations of the claim and the base independent claim, are not disclosed by the prior art of record.
The closest prior arts of record are Belgal et al. (US 20130007344 A1), Ronen (US 20050243626 A1), Kim et al. (US 20200356438 A1), Zeng et al. (US 20170345489 A1), Lee (US 20180081551 A1), Chunn et al. (US 20150169398 A1), Fitzpatrick et al. (US 9543025 B2), and Rotem et al. (US 11029744 B2)
Belgal teaches associating locations in a partition with timestamps and elapsed time. Ronen teaches refreshing memory cells based on a referenced timer. Kim teaches accounting for power off duration in measuring elapsed time since programming a block. Zeng teaches determining read voltage shift to determine power off duration. Lee teaches checking a head or tail region of a block to determine whether a program operation was successful at the time of a power-off. Chun teaches determining temperature, time stamp, and P/E cycle counts during power-on and power-off times. Fitzpatrick teaches determining data decay for estimating power off duration. Rotem teaches calculating a total elapsed lifetime duration of a system comprising active and inactive durations.
However, the prior arts of record, neither individually nor in combination, teaches, with respect to initialization of a block family, initializing a timer at the initialization of the block family and storing a value of the timer while the block family is open prior to powering down the system, where, upon powering up, a value of a data state metric reflecting one of a lower tail location or an upper tail location of a voltage distribution of memory cells of the block family is determined and used for estimating a time after program value of the memory cells, where the value of the timer is incremented based on the obtained time after program value, and, based on the incremented value of the timer, the block family is closed.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim and the base independent claim, the claim as a whole.
With respect to claim 18, “… wherein the data state metric reflects one of a median of a level seven (L7) distribution, a valley location of a level six (L6) distribution, or a valley location of a level seven (L7) distribution.” in conjunction with the other limitations of the claim and the base independent claim, are not disclosed by the prior art of record.
The closest prior arts of record are Belgal et al. (US 20130007344 A1), Ronen (US 20050243626 A1), Kim et al. (US 20200356438 A1), Zeng et al. (US 20170345489 A1), Lee (US 20180081551 A1), Chunn et al. (US 20150169398 A1), Fitzpatrick et al. (US 9543025 B2), and Rotem et al. (US 11029744 B2)
Belgal teaches associating locations in a partition with timestamps and elapsed time. Ronen teaches refreshing memory cells based on a referenced timer. Kim teaches accounting for power off duration in measuring elapsed time since programming a block. Zeng teaches determining read voltage shift to determine power off duration. Lee teaches checking a head or tail region of a block to determine whether a program operation was successful at the time of a power-off. Chun teaches determining temperature, time stamp, and P/E cycle counts during power-on and power-off times. Fitzpatrick teaches determining data decay for estimating power off duration. Rotem teaches calculating a total elapsed lifetime duration of a system comprising active and inactive durations.
However, the prior arts of record, neither individually nor in combination, teaches, with respect to initialization of a block family, initializing a timer at the initialization of the block family and storing a value of the timer while the block family is open prior to powering down the system, where, upon powering up, a value of a data state metric reflecting one of a median of a level seven distribution, a valley location of a level six distribution, or a valley location of a level seven distribution associated with the memory cells of the block family is determined and used for estimating a time after program value of the memory cells, where the value of the timer is incremented based on the obtained time after program value, and, based on the incremented value of the timer, the block family is closed.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim and the base independent claim, the claim as a whole.
Response to Arguments
Applicant’s arguments pertaining to the rejection(s) of claim(s) 1, 8, and 15 as amended under 35 U.S.C. 103 (pages 8-11 of the remarks) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim et al. (US 20160124641 A1) providing for associating a stamp, associated with read voltage offset, with blocks/pages erased simultaneously or within a period of time (para. 55, 59-61, 117-125; figs. 1, 10A-10E and associated paragraphs) (please see the amended rejections above).
Applicant’s arguments with respect to the claim(s) 1, 8, and 15 with respect to the Marelli reference (pages 11-12 of the remarks) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Sutardja (US 7808834 B1) teaches resetting a timer at initiation of an operation such as erase or write operation.
Kuo et al. (US 10403379 B1) teaches performing a reverification operation on an erased block comprising an erased state, the reverification operation utilizing Vra voltage located at an immediately higher voltage level than the erased state voltage threshold.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.Y.K./Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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