DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 13-14 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Kim (US 20100020209 A1).
Regarding Claim 1 Kim discloses an imaging apparatus (imaging device and/or other supported realizations, ¶0204) comprising:
a first semiconductor layer (1300, fig. 13. Also see fig. 3);
a unit cell (4-pixel unit cell of fig. 2, ¶0069-0071) that is provided in the first semiconductor layer (figs. 3, 13, ¶0028) and includes n pixels (4 pixels, figs. 1-2), where n is a natural number (4 is a natural number), and a charge accumulator (FD, fig. 2, ¶0076) in which charge generated in the n pixels accumulates (In this example, the image sensor may accumulate the charges in the FD node through the transferring operation performed N times. – ¶0147); and
a driving circuit (circuit within the apparatus that generates and drives control signals shown in timing diagrams in figs. 5 & 7, e.g.), wherein
each of the n pixels includes:
a photoelectric converter (photodiodes D1-D4, fig. 2);
a first transfer transistor (N11, N21, N31, N41, fig. 2) that includes a first control terminal (respective gates thereof, fig. 2, ¶0078), a first input and output terminal connected to the photoelectric converter (drain of N11, N21, N31, N41 are connected to respective PDs D1-D4, fig. 2, ¶0078), and a second input and output terminal
connected to the charge accumulator (source terminals of N11, N21, N31, N41 are connected to FD node, ¶0078); and
a second transfer transistor (N12, N22, N32, N42, fig. 2) that includes a second control terminal (gates thereof, fig. 2, ¶0074), a third input and output terminal connected to the photoelectric converter (evident from fig. 2), and a fourth input and output terminal different from the third input and output terminal (evident from fig. 2), and
the driving circuit supplies a voltage corresponding to an operation mode selected from among a plurality of operation modes to the first semiconductor layer (Thus, the image sensor may perform a color mode operation and a depth mode operation using a same pixel – ¶0067. Voltages that drives the unit cell of fig. 2 are shown in figs. 5 & 7; specifically note TR1-TR4 & AN_BL), the first control terminal (respective gates of N11, N21, N31, N41, fig. 2, ¶0078), or the second control terminal (respective gates of N12, N22, N32, N42, fig. 2, ¶0078. See descriptions related to operating modes shown in figs. 5 & 7).
Regarding claim 2 Kim discloses the imaging apparatus according to claim 1, wherein the plurality of operation modes include:
a first operation mode in which to expose at least one of the n pixels to light with a first wavelength (fig. 9, ¶0179-0200, claims 2-3); and
a second operation mode in which to expose at least one of the n pixels to blinking light with a second wavelength (fig. 9, ¶0179-0200, claims 2-3).
Regarding claim 3 Kim discloses the imaging apparatus according to claim 1, wherein the driving circuit includes:
a first voltage supply circuit that supplies a voltage to the first semiconductor layer (portions of the circuit that generate RST, ROW IR_Emulsion, and IR_reflection control signals shown in figs. 5, 7); and
a second voltage supply circuit that supplies a voltage to at least one of the first control terminal or the second control terminal (portions of the circuit that generate TR1_TR4 & AN_BL control signals shown in figs. 5, 7).
Regarding claim 13 Kim discloses a distance measuring apparatus comprising:
a light source (Since each pixel may pass infrared light that is reflected by an object, e.g., after being radiated from the imaging device – ¶0066);
the imaging apparatus according to claim 1 (see claim 1 ejection); and
an arithmetic circuit that calculates a distance to a target object in accordance with a signal output from the imaging apparatus (An aspect of one or more embodiments provides a method and apparatus for obtaining a color image expressed by a color and a depth image expressed by a distance, using a single pixel. – ¶0011.
With such dual detection, the image sensor may eliminate an effect that the reflectivity of an object affects the measuring of a distance and generate a depth image based on the depth information corresponding to the first measurement and the depth information corresponding to the second measurement. – ¶0150. Also see ¶0163-0167, ¶0191, claim 43).
Regarding claim 14 Kim discloses a control method for the imaging apparatus according to claim 1, the control method (title, abstract, ¶0011, fig. 4) comprising:
in an operation mode in which to expose at least one of the n pixels to blinking light with a second wavelength, in a period of exposure to the blinking light with the second wavelength (claim 3),
alternating between conduction and nonconduction to avoid simultaneous conduction of the first transfer transistor and the second transfer transistor (evident from fig. 5 timing diagram, see specifically TR1-4 and AN_BL); and
in an operation mode in which to expose at least one of the n pixels to light with a first wavelength, in a period of exposure to the light with the first wavelength (see color image portion of the timing diagram, image is exposed with regular light, fig. 5), maintaining the first transfer transistor and the second transfer transistor in a non-conducting state (see the OFF duration of TR1-4 during color image capture portion of the timing diagram, fig. 5), and causing only the first transfer transistor to enter a conducting state at a predetermined timing (see the ON duration of TR1-4 during color image capture portion of the timing diagram, fig. 5).
Allowable Subject Matter
Claims 4-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior arts of record taken alone or in combination fails to reasonably disclose or suggest,
Regarding claim 4, wherein the driving circuit includes a first voltage supply circuit that supplies a voltage to the first semiconductor layer, and
the first voltage supply circuit includes:
a first signal line set to a first electric potential;
a second signal line set to a second electric potential different from the first electric potential; and
a first connection circuit that switches between the first signal line and the second signal line according to the operation mode and connects the first signal line or the second signal line to the first semiconductor layer.
Claim 5 is allowable for being dependent on allowable claim 4.
Regarding claim 6, wherein the driving circuit includes a second voltage supply circuit that supplies a voltage to at least one of the first control terminal or the second control terminal, and
the second voltage supply circuit includes:
one or more third signal lines set to at least one of a third electric potential or a fourth electric potential higher than the third electric potential;
one or more fourth signal lines set to at least one of a fifth electric potential or a sixth electric potential higher than the fifth electric potential; and
a second connection circuit that switches between the one or more third signal lines and the one or more fourth signal
lines according to the operation mode, and connects the one or more third signal lines or the one or more fourth signal lines to at least one of the first control terminal or the second control terminal.
Claims 7-8 are allowable for being dependent on allowable claim 6.
Regarding claim 9, wherein the driving circuit includes a second voltage supply circuit that supplies a voltage to at least one of the first control terminal or the second control terminal, and
the second voltage supply circuit includes:
a seventh signal line set to a seventh electric potential;
an eighth signal line set to an eighth electric potential different from the seventh electric potential; and
a third connection circuit that switches between the seventh signal line and the eighth signal line according to the operation mode, and connects the seventh signal line or the eighth signal line to at least one of the first control terminal or the second control terminal.
Claim 10 is allowable for being dependent on allowable claim 9.
Regarding claim 11, wherein the unit cell includes:
a capacitor that includes a first electrode and a second electrode; and
a switching device connected in series between the first electrode and the charge accumulator, and
the switching device maintains conduction between the capacitor and the charge accumulator in the second operation mode, and interrupts conduction between the capacitor and the charge accumulator in the first operation mode.
Claim 12 is allowable for being dependent on allowable claim 11.
Conclusion
The prior and/or pertinent art(s) made of record and not relied upon is considered pertinent to applicant's disclosure, are – Seta (US 20240272284 A1), Jin (US 20240276112 A1), Akahori et al. (US 11982750 B2), Ebiko (US 20230261029 A1), Tdmor et al. (US 20210337149 A1) – who disclose hybrid type color and depth/distance image sensor architectures of interest.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHBAZ NAZRUL whose telephone number is (571)270-1467. The examiner can normally be reached M-Th: 9.30 am-3 pm, 6.30 pm-9 pm, F: 9.30 am-1.30 pm, 4 pm-8 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAHBAZ NAZRUL/Primary Examiner, Art Unit 2638
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