DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted 3/21/2025 is in compliance with the provisions of 37 CFR 1.97 and being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2020/0366264, published 11/19/2020 (“Nakashima”).
Nakashima discloses in Figs. 1-7 and the corresponding description:
Claim 1
A multilayered branching filter (Figs. 1-7, multilayer triplexer 100, ¶¶33-143) comprising:
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a common terminal (Figs. 5-6, 2a);
a first signal terminal (3a or 3b);
a second signal terminal (3c);
a first path (Fig. 5, low-band signal path 21 or middle-band signal path 22) connecting the common terminal (2a) and the first signal terminal (3a or 3b) to each other;
a second path (high-band signal path 23) connecting the common terminal (2a) and the second signal terminal (3c) to each other;
a first inductor (Figs. 2-6, inductor L3 or L9) provided between the common terminal (2a) and the second signal terminal (3c) in a circuit configuration; and
a stack for integrating the common terminal, the first signal terminal, the second signal terminal, the first path, the second path, and the first inductor, the stack including a plurality of dielectric layers being stacked (Figs. 2-4, dielectric layers 1a-1aa), wherein
the first path (21 or 22) is configured to selectively cause a signal having a frequency within a first passband to pass (¶93, low-band signal path 21 or middle-band signal path 22),
the second path is configured to selectively cause a signal having a frequency within a second passband to pass, the second passband being different from the first passband (¶93, high-band signal path 23),
the stack further includes a first region (Fig. 6, annotated, “first region” or “third region” as indicated with dashed lines) and a second region (Fig. 6, “second region”) that are adjacent within the stack, and includes a first structure body (Fig. 6, “first structure body” indicated with dotted lines) that is arranged in a vicinity of a boundary between the first region and the second region and is connected to a ground (at least some of the sub-structure bodies of the first structure body are arranged in a vicinity of a boundary between the first/third region and the second region and are connected to ground electrode 5a),
the first structure body includes a plurality of first sub structure bodies (¶¶124, 129; a plurality of via conductors, coil conductor patterns and electrodes connected to and defining inductors L3 or L9) that are stacked in a direction parallel to a stacking direction of the plurality of dielectric layers (Figs. 2-7),
each of the plurality of first sub structure bodies includes a plurality of first through holes (¶124, via conductors 9ab, 9bd, 9bi, 9bs connected to inductor L3; ¶129, via conductors 9b1, 9aw, 9ar, 9am, 9q connected to inductor L9) and a first conductor layer (¶124, relay electrode 6l and coil conductor patterns 8r, 8x, 8ah of inductor L3; ¶129, electrode 6j and coil conductor patterns 8l, 8h, 8d of inductor L9) that connects the plurality of first through holes (Figs. 2-5), and
the first inductor (L3 or L9) is arranged in the second region (Figs. 2-6), and is connected to the first structure body (¶¶124, 129).
Because Nakashima discloses a triplexer including three filters disposed in three adjacent regions, it discloses several alternatives meeting the claim limitations. For example, “first path” can be met by either path 21 or path 22, as set forth above. Similarly, “first region” can be met by either “first region” or “third region” as indicated with dashed lines in Fig. 6 annotated.
Claim 2
further comprising:
a first filter (Fig. 5, LPF defined by L1, L4-L5 and C1-C4; or HPF defined by L2, L6, C5-C7) provided to the first path (21 or 22); and
a second filter (Fig. 5, HPF defined by L3, L9, C11-C12) provided to the second path (23), wherein
the first filter is arranged in the first region (for LPF defined by L1, L4-L5 and C1-C4, the corresponding region is indicated as “first region” in Fig. 6, annotated, ¶¶95-110; for HPF defined by L2, L6, C5-C7, the corresponding region is indicated as “third region” in Fig. 6, annotated, ¶¶111-122), and
the second filter includes the first inductor (inductor L3 or L9), and is arranged in the second region (Figs. 2-6, ¶¶123-133).
Because Nakashima discloses a triplexer including three filters disposed in three adjacent regions, it discloses several alternatives meeting the claim limitations. For example, “first filter” can be met by certain elements of filter 31 (annotated as “first filter” in Fig. 6 above) or filter 32 (annotated as “third filter” in Fig. 6 above).
Claim 3
wherein both the first filter (HPF defined by L2, L6, C5-C7) and the second filter (HPF defined by L3, L9, C11-C12) are high-pass filters.
Claim 4
wherein the first filter is a low-pass filter (LPF defined by L1, L4 and L5 and C1-C4), and the second filter is a high-pass filter (HPF defined by L3, L9, C11-C12).
Claim 5
further comprising:
a third signal terminal (Fig. 5, terminal 3b);
a third path (middle-band signal path 22) connecting the common terminal (2a) and the third signal terminal (3b) to each other; and
a second inductor (Figs. 2-6, inductor L2 or L6) provided between the common terminal (2a) and the third signal terminal (3b) in the circuit configuration, wherein
the third path is configured to selectively cause a signal having a frequency within a third passband to pass, the third passband being different from each of the first passband and the second passband (¶93, middle-band signal path 22),
the stack further includes a third region (Fig. 6, indicated with dashed lines in plan view) adjacent to the second region within the stack, and includes a second structure body (Fig. 6, indicated with dotted lines) that is arranged in a vicinity of a boundary between the second region and the third region and is connected to the ground (at least some of the identified below sub-structure bodies of the second structure body are arranged in a vicinity of a boundary between the second region and the third region and are connected to ground electrode 5a),
the second structure body includes a plurality of second sub structure bodies (¶¶112, 116; a plurality of via conductors, coil conductor patterns and electrodes connected to and defining inductors L2 or L6) that are stacked in the direction parallel to the stacking direction,
each of the plurality of second sub structure bodies includes a plurality of second through holes (¶112, via conductors 9ab, 9bp, 9bg, 9au, 9ai connected to inductor L2; ¶116, via conductors 9af, 9aq, 9av, 9bc, 9bh, 9n connected to inductor L6) and a second conductor layer (¶112, electrode 6k, coil conductor patterns 8m, 8ag, 8v, 8j of inductor L2; ¶116, coil conductor patterns 8g, 8k, 8q, 8w, 8ac of inductor L6) that connects the plurality of second through holes, and
the second inductor (L2 or L6) is arranged in the third region (Figs. 2-6), and is connected to the second structure body (¶¶112, 116).
Claim 6
further comprising:
a first filter (LPF defined by L1, L4 and L5 and C1-C4) provided to the first path (21); and
a second filter (HPF defined by L3, L9, C11-C12) provided to the second path (23), and
a third filter (HPF defined by L2, L6, C5-C7) provided to the third path (22), wherein
the first filter is arranged in the first region (Figs. 2-6, ¶¶95-110),
the second filter includes the first inductor (inductors L3 or L9), and is arranged in the second region (Figs. 2-6, ¶¶123-133); and
the third filter includes the second inductor (inductor L2 or L6), and is arranged in the third region (Figs. 2-6, ¶¶111-122).
Claim 7
wherein the first filter is a low-pass filter (Fig. 5, LPF defined by L1, L4 and L5 and C1-C4) and
the second filter and the third filter are a high-pass filter (second filter is an HPF defined by L3, L9, C11-C12; third filter is an HPF defined by L2, L6, C5-C7).
Claim 8
wherein the first structure body is connected to a specific conductor layer for forming an element different from the first inductor (¶124, first structure body is connected through via conductor 9bs to the capacitor electrode 7aa of capacitor C11; ¶129, first structure body is connected through via conductor 9q to the ground electrode 5a).
Claim 9
the first structure body includes a first end (Fig. 4, end of via conductor 9b1 at the point of connection to capacitor electrode 7ac) and a second end (Fig. 2, end of via conductor 9q at the point of connection to ground electrode 5a) that are positioned on opposite sides in the stacking direction (Figs. 2-4), and
the specific conductor layer is connected to the first structure body between the first end and the second end (capacitor electrode 7aa is connected to the first structure body between the capacitor electrode 7ac and ground electrode 5a).
Claim 10
wherein the specific conductor layer includes a capacitor conductor layer for forming a capacitor (¶124, first structure body is connected through via conductor 9bs to the capacitor electrode 7aa of capacitor C11).
Claim 11
the first structure body is arranged in the second region (Figs. 2-6, ¶¶124, 129), and
the specific conductor layer extends from the first structure body to the first region (Fig. 2, ¶129, first structure body is connected through via conductor 9q to the ground electrode 5a, which extends to the first region).
Claim 12
wherein a part of the first inductor overlaps with the first structure body as viewed in the stacking direction (Figs. 2-6, ¶¶124, 129, first structure body overlaps inductors l3 and L9 in plan view).
Claim 13
the first inductor includes an inductor conductor layer (¶124, coil conductor patterns 8r, 8x, 8ah of inductor L3; ¶129, coil conductor patterns 8l, 8h, 8d of inductor L9),
the plurality of first sub structure bodies include a specific first sub structure body positioned at an end in one direction parallel to the stacking direction (for example, vias 9ab and 9bd connected by coil conductor pattern 8r or vias 9bd and 9bi connected by coil conductor pattern 8x or vias 9bi and 9bs connected by coil conductor pattern 8ah), and
the inductor conductor layer and the first conductor layer of the specific sub structure body are arranged at the same position in the stacking direction (the coil conductors patterns are arranged at the same position in the stacking direction.)
Claim 14
another inductor (Fig. 5, L1, L4 or L5 of LPF defined by L1, L4-L5; L2 or L6 of HPF defined by L2, L6, C5-C7) provided between the common terminal (2a) and the first signal terminal (3a or 3b) in the circuit configuration, and
the other inductor (L1, L4, L5 or L2, L6) is arranged in the first region (Figs 2-6, ¶¶104-106).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication No. 2022/0294411, published 9/15/2022 (“Sato”) discloses a multilayer triplexer including a common port, three signal ports, three signal paths, three filters each with at least one inductor disposed in respective regions, three structure bodies with sub-structure bodies including via and connecting conductor layers (Figs. 1-11, ¶¶37-98).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR COLE, telephone number (571) 272-4686. The examiner can be reached Monday-Friday, 9AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDREA LINDGREN BALTZELL, can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/VICTOR COLE/
Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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