DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been presented and pending in the application.
Allowable Subject Matter
Claims 15-20 are allowable over the prior art of record when the claim 15 overcomes the following rejection under 35 U.S.C. 112. The prior art of record does not teach the recited detailed combinations of the claimed structural and functional inter-couplings of the “switch driver circuit” & “control circuit”; therefore, allowable over the prior art of record.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Claims 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1:
In line 3, the phrase “to be connected between a first voltage level and a terminal” are vague and indefinite as to how each switches and resistors are actually connected. The “voltage” and “terminal” are not utilized by the claimed invention; therefore, the above phrase is vaguer and indefinite.
In lines 4-6, it unclear and unstated as to how each switches and resistors are actually connected to the control circuit for performing “enable” & “disable” each and every switches; therefore, clear metes and bounds of the claimed invention is unclear and indefinite from the claimed invention.
In lines 9-10, the phrase “enablement of the switch of the given”” is not supported from the context of the claimed invention (i.e., no support for the enablement is provided by the claimed invention other than “configured to” in line 4). The phrase “resistor” lacks proper and clear antecedent basis.
In lines 11-12, the phrase “disablement of the switch of the given” is not supported from the context of the claimed invention (i.e., no support for the disablement is provided by the claimed invention other than “configured to” in line 4). The phrase “resistor” lacks proper and clear antecedent basis.
In line 13, The phrase “resistor” & “switch” lack proper and clear antecedent basis.
In claim 2:
In line 3, the support for the phrase “target output impedance value” is unstated or unclear from the claimed invention (i.e., how does the controller connected to each and every switches to support such the phrase?).
In claim 3:
In lines 1-4, the support for the phrase “output value on the terminal to have a designated output impedance to accommodate a variance of process voltage, or temperature” is unstated or unclear from the claimed invention (i.e., how does the controller connected to each and every switches to support such the phrase?).
In claim 4:
In lines 2-5, the support for the phrase “first output impedance that is lower than an initial output impedance” is unstated or unclear from the claimed invention (i.e., how does the controller connected to connected to each and every switches to support such the phrase?).
In line 4, the phrase “respective switches of the plurality of switch-resistor pairs are disabled” lacks proper and clear antecedent basis.
In lines 6-8, the support for the phrase “second output impedance that is higher than the initial output impedance” is unstated or unclear from the claimed invention (i.e., how does the controller connected to connected to each and every switches to support such the phrase?).
In lines 4 and 7, it is unclear and unstated as to how the higher than the initial output impedance can be supported by performing the identical operation/function (i.e., disable respective switches; the initial value was already produced by the disablement of the switches).
In claim 5:
In line 2, the phrase “control circuit enables the first network of the plurality of switch-resistor pairs” lacks proper and clear antecedent basis
In claim 6:
In lines 1-12, the unclarities of the claim 1 are similarly applied.
Ine lines 5-6, the phrase “enable the first network of the plurality of switch-resistor pairs to produce the first voltage level” lacks proper and clear antecedent basis.
In lines 8-9, the phrase “enable the second network of the plurality of switch-resistor pairs to produce the second voltage level” lacks proper and clear antecedent basis.
In lines 6 & 9, it is unclear and unstated as to how the same “terminal” has two different voltage values when the first and second are both enabled, as claimed.
In line 11, the “output impedance when outputting the logical one value or logical zero value” lacks proper and clear antecedent basis.
In claims 8:
In line 2, it is unclear and unstated as to who or what performs “operating” step/function.
In line 7, it is unclear and unstated as to who or what performs “enabling” step/function.
In line 10, it is unclear and unstated as to who or what performs “disabling” step/function.
In lines 1-14, the above unclarities of the claim 1 are similarly applied, due to the similarity between the claims 1 and 8.
In claims 9-13:
The above discussed unclarities of the claims 2-6 are similarly applied.
In claim 15:
In line 12, the “terminal’ lacks proper and clear antecedent basis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-14 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by IKEDA (US 2017/0315572).
Examiner relies on the entire teachings of IKEDA reference for this rejection; hence, the examiner advises the applicant to carefully consider the entire teachings of the IKEDA reference to better understand the examiner’s position and Broadest Reasonable Interpretation applied to the claimed invention.
The IKEDA reference teaches, as best understood by the examiner due to the numerous unclarities and indefiniteness of the claimed invention, the claimed invention is a system/method of using switch and resistor pairs to control impedance values by switching (i.e., enable/disable) switches on and off. Clearly, in figures 1-2 & 6 with accompanying description of, the IKEDA reference teaches the best understood claimed invention. Therefore, the claimed invention is clearly anticipated by the IKEDA reference teachings, as discussed above.
Claims 1-14 are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by MIYASHITA (US 2024/0088854 A1).
Examiner relies on the entire teachings of MIYASHITA reference for this rejection; hence, the examiner advises the applicant to carefully consider the entire teachings of the MIYASHITA reference to better understand the examiner’s position and Broadest Reasonable Interpretation applied to the claimed invention.
The MIYASHITA reference teaches, as best understood by the examiner due to the numerous unclarities and indefiniteness of the claimed invention, the claimed invention is a system/method of using switch and resistor pairs to control impedance values by switching (i.e., enable/disable) switches on and off. Clearly, in figures 2-3, 5, 7, 9 and/or 11-12 with accompanying descriptions of, the MIYASHITA reference teaches the best understood claimed invention. Therefore, the claimed invention is clearly anticipated by the MIYASHITA reference teachings, as discussed above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER B SHIN whose telephone number is (571)272-4159. The examiner can normally be reached 8:00-4:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached at 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER B SHIN/Primary Examiner, Art Unit 2181
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