DETAILED ACTION
The instant application having Application No. 19/086,523 has a total of 20 claims pending in the application, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made of applicant’s claim for foreign priority based on an application filed in PEOPLE’S REPUBLIC OF CHINA on 9/23/2022. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Language
Claims 3-8 and 10 recite limitations which, as claimed, are conditionally executed without accounting for the possibility of the condition failing to trigger.
The limitations in the claims following “when” are not positively recited in the claims, as the limitations, as claimed, are conditionally executed without accounting for the possibility of the condition failing to occur. The method may never be required to execute the conditions because “when” is a temporal conditional precedent that may never be reached within the scope of the claim under the broadest reasonable interpretation. The examiner recommends amending the instances of limitations reliant on the language reciting “when” to instead recite “in response to” and further providing a positive recitation of the relevant condition occurring.
For instance, the examiner recommends amending claim 5 as:
5. The method of claim 1, wherein obtaining the data migration request comprises: performing data migration detection on the first storage medium; detecting that the first storage unit meets a migration condition; and generating the data migration request [[when]] in response to the first storage unit [[meets]] meeting [[a]] the migration condition.
See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding “The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim”); see also Ex parte Katz, Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original.
Claim Objections
Claims 13, 15-18 are objected to because of the following informalities:
The examiner suggests amending a limitation in claim 13 reciting, “the first address comprises modifying the second address in the mapping relationship to a third during eligibility address of the second storage unit.”, as “the first address comprises modifying the second address in the mapping relationship to a third [[during eligibility]] address of the second storage unit.”
The examiner suggests amending a limitation in claim 15, reciting “wherein "the second data read request indicates to read the data from the second cache line.”, as “wherein [["the]] the second data read request indicates to read the data from the second cache line.”
Claims 16-18 are objected for being based on an objected claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 17-18 recite “wherein the program code to perform data migration detection on the first storage medium comprises”. However, there is insufficient antecedent basis for this term or subject matter involving the program code to perform data migration detection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 8-9, 11-14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jayasena et al. (US 20150199126 A1) in view of Kanno (US 20180247948 A1) in view of Sugimoto et al. (US 20110231594 A1).
As per claim 1,
1. A method comprising: obtaining a data migration request to migrate data from a first storage unit in a first storage medium of a hybrid memory system to a second storage medium of the hybrid memory system; migrating the data from the first storage unit to a second storage unit in the second storage medium in response to the request, [Jayasena teaches a system comprising different memory types and logic die comprising a processor and hardware logic including migration manager and memory interface (para. 35, 14, 22-23, 67-68), where the migration manager may autonomously facilitate migration of memory pages from one memory to another (e.g. between a faster memory (first storage medium) to a slower memory (second storage medium)) (para. 37, 42, 58-62, 15, 38; figs. 3, 6 and associated paragraphs) by providing control information (data migration request) (para. 36, 62, 72)]
Jayasena does not explicitly disclose, but Kanno discloses:
allocating, to the second storage unit, a first address associated with the first storage unit during the unified addressing. [Jayasena as shown above teaches performing migration and also teaches updating mapping pursuant to the migration (para. 62); Kanno teaches copying data from a source block of a source NVM set to a destination NVM set, the process including allocating a destination block from a free block pool of the destination NVM set for receiving the data, and updating the mapping between logical addresses (first address) of the data transferred from the source block so that the logical addresses are updated to map to physical addresses of the destination block instead of the physical addresses of the source block (para. 98; figs. 2, 10 and associated paragraphs)]
Jayasena and Kanno are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena and Kanno, to modify the disclosures by Jayasena to include disclosures by Kanno since they both teach data storage and memory access, wherein Kanno is directed towards improved wear management (para. 2-7). Therefore, it would be applying a known technique (allocating a free block for a migration destination addresses while remapping migration source locations to destination locations) to a known device (memory device performing migration between memories having different speeds) ready for improvement to yield predictable results (memory device performing migration between memories having different speeds, the migration involving allocating a free block for a migration destination addresses while remapping migration source locations to destination locations in order to provide for continuity of access to migrated data). MPEP 2143
Jayasena in view of Kanno does not explicitly disclose, but Sugimoto discloses:
wherein the second storage unit does not participate in unified addressing in the hybrid memory system; and [Jayasena in view of Kanno as shown above teaches allocating free blocks for destination locations; it does not explicitly disclose, but Sugimoto teaches free blocks comprising blocks that have been erased and unmapped (para. 44-50)]
Jayasena, Kanno, and Sugimoto are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena in view of Kanno and Sugimoto, to modify the disclosures by Jayasena in view of Kanno to include disclosures by Sugimoto since they both teach data storage and memory access, wherein Sugimoto is directed towards improved block allocation and wear leveling (para. 13-15). Therefore, it would be applying a known technique (free blocks comprising unmapped and erased blocks) to a known device (allocating free blocks for data migration) ready for improvement to yield predictable results (allocating free blocks for data migration, the free blocks comprising unmapped and erased blocks in order to provide for reduced mapping overhead in assigning new data and addresses to free blocks being used). MPEP 2143
As per claim 2, Jayasena in view of Kanno in view of Sugimoto teaches claim 1 as shown above and further teaches:
2. The method of claim 1, further comprising allocating, based on a mapping relationship between the first address and a second address of the first storage unit, the first address to the first storage unit, wherein allocating, to the second storage unit, the first address comprises modifying the second address in the mapping relationship to a third address of the second storage unit. [Jayasena in view of Kanno in view of Sugimoto as shown above teaches remapping logical addresses (first address) of migrated data to correspond to physical addresses of the destination memory (third address) from the physical addresses of the source memory (second address) (see above; Kanno: para. 98)]
Jayasena and Kanno are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena and Kanno, to modify the disclosures by Jayasena to include disclosures by Kanno since they both teach data storage and memory access, wherein Kanno is directed towards improved wear management (para. 2-7). Therefore, it would be applying a known technique (allocating a free block for a migration destination addresses while remapping migration source locations to destination locations) to a known device (memory device performing migration between memories having different speeds) ready for improvement to yield predictable results (memory device performing migration between memories having different speeds, the migration involving allocating a free block for a migration destination addresses while remapping migration source locations to destination locations in order to provide for continuity of access to migrated data). MPEP 2143
As per claim 3, Jayasena in view of Kanno in view of Sugimoto teaches claim 1 as shown above and further teaches:
3. The method of claim 1, further comprising: receiving a first data write request of an application, wherein the first data write request indicates to write the data into the first storage unit; querying a migration state of the first storage unit based on the first data write request, wherein the migration state indicates a migration progress of the first storage unit; and converting, when the migration state indicates that the data in the first storage unit is being migrated to the second storage unit, the first data write request into a second data write request, wherein the second data write request indicates to write the data into the second storage unit. [Jayasena teaches an external device having software/applications and sending memory access requests (para. 59-60, 63-64; figs. 6-7 and associated paragraphs), where the memory access requests may be received in parallel with performing page migration, and memory access of a request may be determined to be directed to a page that has been migrated based on a comparison the request’s address against migration information variables, where the request address may be modified and memory access is performed (para. 66, 64)]
As per claim 5, Jayasena in view of Kanno in view of Sugimoto teaches claim 1 as shown above and further teaches:
5. The method of claim 1, wherein obtaining the data migration request comprises: performing data migration detection on the first storage medium; and generating the data migration request when the first storage unit meets a migration condition. [Jayasena as shown above teaches providing control information for migrating data pages (see claim 1 above) and further teaches monitoring memory accesses for updating memory usage information, such as access frequency, used for page migrations between slow and faster memory (para. 27, 15, 49-40; see para. 14, 24 on memory accesses performed responsive to memory access requests from an external device having software/applications), where pages may be migrated based on conditions such as the pages’ access frequency falling below a lower threshold or above an upper threshold (para. 59, 52-53)]
As per claim 6, Jayasena in view of Kanno in view of Sugimoto teaches claim 5 as shown above and further teaches:
6. The method of claim 5, wherein the first storage unit meets the migration condition when a quantity of accesses to the first storage unit reaches a value range of a migration threshold, and wherein performing data migration detection on the first storage medium comprises: detecting a data access request of the hybrid memory system, wherein the data access request indicates to access a storage unit in the hybrid memory system; and obtaining, based on the data access request, the quantity of accesses to the first storage unit. [Jayasena as shown above teaches providing control information for migrating data pages (see claims 1, 5 above) and further teaches monitoring memory accesses for updating memory usage information, such as access frequency, used for page migrations between slow and faster memory (para. 27, 15, 49-40; see para. 14, 24 on memory accesses performed responsive to memory access requests from an external device having software/applications), where pages may be migrated based on conditions such as the pages’ access frequency falling below a lower threshold or above an upper threshold (para. 59, 52-53), where, if the first storage unit is so accessed and has its memory usage information updated, the first storage unit may correspond to ‘a storage unit’ as well]
As per claim 8, Jayasena in view of Kanno in view of Sugimoto teaches claim 5 as shown above and further teaches:
8. The method of claim 5, further comprising: receiving a data access request of an application for the first storage unit; and generating, in response to the data access request, the data migration request when the first storage unit meets the migration condition. [Jayasena as shown above teaches providing control information for migrating data pages (see claims 1, 5 above) and further teaches monitoring memory accesses for updating memory usage information, such as access frequency, used for page migrations between slow and faster memory (para. 27, 15, 49-40; see para. 14, 24 on memory accesses performed responsive to memory access requests from an external device having software/applications), where pages may be migrated based on conditions such as the pages’ access frequency falling below a lower threshold or above an upper threshold (para. 59, 52-53; see claim 5 above)]
As per claim 9, Jayasena in view of Kanno in view of Sugimoto teaches claim 1 as shown above and further teaches:
9. The method of claim 1, further comprising determining, prior to migrating the data in the first storage unit to the second storage unit in the second storage medium, the second storage unit from a candidate storage unit in the second storage medium, wherein the candidate storage unit is a first idle storage unit that does not participate in the unified addressing. [Jayasena in view of Kanno in view of Sugimoto as shown above teaches allocating a free block from a free block pool of the destination memory, where free blocks are erased and unmapped (see claim 1 above; Kanno: para. 98; Sugimoto: para. 44-50)]
Jayasena and Kanno are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena and Kanno, to modify the disclosures by Jayasena to include disclosures by Kanno since they both teach data storage and memory access, wherein Kanno is directed towards improved wear management (para. 2-7). Therefore, it would be applying a known technique (allocating a free block for a migration destination addresses while remapping migration source locations to destination locations) to a known device (memory device performing migration between memories having different speeds) ready for improvement to yield predictable results (memory device performing migration between memories having different speeds, the migration involving allocating a free block for a migration destination addresses while remapping migration source locations to destination locations in order to provide for continuity of access to migrated data). MPEP 2143
Jayasena, Kanno, and Sugimoto are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena in view of Kanno and Sugimoto, to modify the disclosures by Jayasena in view of Kanno to include disclosures by Sugimoto since they both teach data storage and memory access, wherein Sugimoto is directed towards improved block allocation and wear leveling (para. 13-15). Therefore, it would be applying a known technique (free blocks comprising unmapped and erased blocks) to a known device (allocating free blocks for data migration) ready for improvement to yield predictable results (allocating free blocks for data migration, the free blocks comprising unmapped and erased blocks in order to provide for reduced mapping overhead in assigning new data and addresses to free blocks being used). MPEP 2143
As per claim 11,
11. A data migration apparatus comprising: a memory configured to store instructions; one or more processors configured to execute the instructions to cause the data migration apparatus to: obtain a data migration request to migrate data from a first storage unit in a first storage medium of a hybrid memory system to a second storage medium of the hybrid memory system; migrate the data in the first storage unit to a second storage unit in the second storage medium, [Jayasena teaches a system comprising different memory types and logic die comprising a processor and hardware logic including migration manager and memory interface (para. 35, 14, 22-23, 67-68), where the migration manager may autonomously facilitate migration of memory pages from one memory to another (e.g. between a faster memory (first storage medium) to a slower memory (second storage medium)) (para. 37, 42, 58-62, 15, 38; figs. 3, 6 and associated paragraphs) by providing control information (data migration request) (para. 36, 62, 72)]
Jayasena does not explicitly disclose, but Kanno discloses:
allocate, to the second storage unit, a first address associated with the first storage unit during the unified addressing. [Jayasena as shown above teaches performing migration and also teaches updating mapping pursuant to the migration (para. 62); Kanno teaches copying data from a source block of a source NVM set to a destination NVM set, the process including allocating a destination block from a free block pool of the destination NVM set for receiving the data, and updating the mapping between logical addresses (first address) of the data transferred from the source block so that the logical addresses are updated to map to physical addresses of the destination block instead of the physical addresses of the source block (para. 98; figs. 2, 10 and associated paragraphs)]
Jayasena and Kanno are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena and Kanno, to modify the disclosures by Jayasena to include disclosures by Kanno since they both teach data storage and memory access, wherein Kanno is directed towards improved wear management (para. 2-7). Therefore, it would be applying a known technique (allocating a free block for a migration destination addresses while remapping migration source locations to destination locations) to a known device (memory device performing migration between memories having different speeds) ready for improvement to yield predictable results (memory device performing migration between memories having different speeds, the migration involving allocating a free block for a migration destination addresses while remapping migration source locations to destination locations in order to provide for continuity of access to migrated data). MPEP 2143
Jayasena in view of Kanno does not explicitly disclose, but Sugimoto discloses:
wherein the second storage unit does not participate in unified addressing in the hybrid memory system; and [Jayasena in view of Kanno as shown above teaches allocating free blocks for destination locations; it does not explicitly disclose, but Sugimoto teaches free blocks comprising blocks that have been erased and unmapped (para. 44-50)]
Jayasena, Kanno, and Sugimoto are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena in view of Kanno and Sugimoto, to modify the disclosures by Jayasena in view of Kanno to include disclosures by Sugimoto since they both teach data storage and memory access, wherein Sugimoto is directed towards improved block allocation and wear leveling (para. 13-15). Therefore, it would be applying a known technique (free blocks comprising unmapped and erased blocks) to a known device (allocating free blocks for data migration) ready for improvement to yield predictable results (allocating free blocks for data migration, the free blocks comprising unmapped and erased blocks in order to provide for reduced mapping overhead in assigning new data and addresses to free blocks being used). MPEP 2143
As per claim 12,
12. A chip comprising: a processor configured to execute program code to cause the chip to: obtain a data migration request to migrate data from a first storage unit in a first storage medium of a hybrid memory system to a second storage medium of the hybrid memory system; migrate the data from the first storage unit to a second storage unit in the second storage medium in response to the request, [Jayasena teaches a system comprising different memory types and logic die comprising a processor and hardware logic including migration manager and memory interface (para. 35, 14, 22-23, 67-68), where the migration manager may autonomously facilitate migration of memory pages from one memory to another (e.g. between a faster memory (first storage medium) to a slower memory (second storage medium)) (para. 37, 42, 58-62, 15, 38; figs. 3, 6 and associated paragraphs) by providing control information (data migration request) (para. 36, 62, 72)]
Jayasena does not explicitly disclose, but Kanno discloses:
allocate, to the second storage unit, a first address associated with the first storage unit during the unified addressing. [Jayasena as shown above teaches performing migration and also teaches updating mapping pursuant to the migration (para. 62); Kanno teaches copying data from a source block of a source NVM set to a destination NVM set, the process including allocating a destination block from a free block pool of the destination NVM set for receiving the data, and updating the mapping between logical addresses (first address) of the data transferred from the source block so that the logical addresses are updated to map to physical addresses of the destination block instead of the physical addresses of the source block (para. 98; figs. 2, 10 and associated paragraphs)]
Jayasena and Kanno are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena and Kanno, to modify the disclosures by Jayasena to include disclosures by Kanno since they both teach data storage and memory access, wherein Kanno is directed towards improved wear management (para. 2-7). Therefore, it would be applying a known technique (allocating a free block for a migration destination addresses while remapping migration source locations to destination locations) to a known device (memory device performing migration between memories having different speeds) ready for improvement to yield predictable results (memory device performing migration between memories having different speeds, the migration involving allocating a free block for a migration destination addresses while remapping migration source locations to destination locations in order to provide for continuity of access to migrated data). MPEP 2143
Jayasena in view of Kanno does not explicitly disclose, but Sugimoto discloses:
wherein the second storage unit does not participate in unified addressing in the hybrid memory system; and [Jayasena in view of Kanno as shown above teaches allocating free blocks for destination locations; it does not explicitly disclose, but Sugimoto teaches free blocks comprising blocks that have been erased and unmapped (para. 44-50)]
Jayasena, Kanno, and Sugimoto are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena in view of Kanno and Sugimoto, to modify the disclosures by Jayasena in view of Kanno to include disclosures by Sugimoto since they both teach data storage and memory access, wherein Sugimoto is directed towards improved block allocation and wear leveling (para. 13-15). Therefore, it would be applying a known technique (free blocks comprising unmapped and erased blocks) to a known device (allocating free blocks for data migration) ready for improvement to yield predictable results (allocating free blocks for data migration, the free blocks comprising unmapped and erased blocks in order to provide for reduced mapping overhead in assigning new data and addresses to free blocks being used). MPEP 2143
Claim 13 is rejected for reasons similar to claim 2.
Claim 14 is rejected for reasons similar to claim 3.
Claim 19 is rejected for reasons similar to claim 9.
Claims 4 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jayasena et al. (US 20150199126 A1) in view of Kanno (US 20180247948 A1) in view of Sugimoto et al. (US 20110231594 A1) in view of Ray et al. (US 20170192714 A1).
As per claim 4, Jayasena in view of Kanno in view of Sugimoto teaches claim 1 as shown above. It does not explicitly disclose, but Ray discloses:
4. The method of claim 1, further comprising: receiving a first data read request of an application, wherein the first data read request indicates to read the data from a first cache line of the first storage unit; obtaining, based on the first data read request, a write state of a second cache line that is of the second storage unit and that corresponds to the first cache line, wherein the write state indicates progress of writing the data into the second cache line; and converting, when the write state indicates that the data has been written into the second cache line, the first data read request into a second data read request, wherein the second data read request indicates to read the data from the second cache line. [Where Jayasena in view of Kanno in view of Sugimoto as shown above teaches migrating data from source locations of a memory to destination locations of memory (see claim 1 above); Ray teaches migrating of data from a source stripe to a destination stripe (para. 13, 33; figs. 1, 3 and associated paragraphs), where data from the data cache line of the source stripe may be read and written to the data cache line of the destination stripe, and a data-migrated token may be written to the data cache line of the source stripe (para. 39-40, 43, 46; figs. 3, 4 and associated paragraphs); a read (first data read request) directed to the source stripe may return said data-migrated token as stored in the data cache of the source stripe, and a redundancy controller may responsibly initiate a read (second data read request) of the migrated data from the data cache line of the destination stripe in response to receiving the data-migrated token (para. 49; fig. 6 and associated paragraphs)]
Jayasena, Kanno, Sugimoto, and Ray are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena in view of Kanno in view of Sugimoto and Ray, to modify the disclosures by Jayasena in view of Kanno in view of Sugimoto to include disclosures by Ray since they both teach data storage and memory access, wherein Ray is directed towards improved data migration and preventing data corruption (para. 1). Therefore, it would be applying a known technique (providing token in cache of migrated source location; initiating a read on the destination cache responsive to retrieving the token) to a known device (device performing data migration between memories) ready for improvement to yield predictable results (device performing data migration between memories, where a token in stored to the caches of migrated source locations, and, responsive to retrieving the token from a read, another read is initiated for the destination cache in order to provide for a method for quickly establishing temporary read redirects). MPEP 2143
As per claim 15, Jayasena in view of Kanno in view of Sugimoto teaches claim 12 as shown above. It does not explicitly disclose, but Ray discloses:
15. The chip of claim 12, wherein the processor is configured to execute the program code to further cause the chip to: receive a first data read request of an application, wherein the first data read request indicates to read the data from a first cache line of the first storage unit; obtain, based on the first data read request, a write state of a second cache line that is of the second storage unit and that corresponds to the first cache line, wherein the write state indicates progress of writing the data into the second cache line; and convert, when the write state indicates that the data has been written into the second cache line, the first data read request into a second data read request, wherein "the second data read request indicates to read the data from the second cache line. [Where Jayasena in view of Kanno in view of Sugimoto as shown above teaches migrating data from source locations of a memory to destination locations of memory (see claim 12 above); Ray teaches migrating of data from a source stripe to a destination stripe (para. 13, 33; figs. 1, 3 and associated paragraphs), where data from the data cache line of the source stripe may be read and written to the data cache line of the destination stripe, and a data-migrated token may be written to the data cache line of the source stripe (para. 39-40, 43, 46; figs. 3, 4 and associated paragraphs); a read (first data read request) directed to the source stripe may return said data-migrated token as stored in the data cache of the source stripe, and a redundancy controller may responsibly initiate a read (second data read request) of the migrated data from the data cache line of the destination stripe in response to receiving the data-migrated token (para. 49; fig. 6 and associated paragraphs)]
Jayasena, Kanno, Sugimoto, and Ray are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena in view of Kanno in view of Sugimoto and Ray, to modify the disclosures by Jayasena in view of Kanno in view of Sugimoto to include disclosures by Ray since they both teach data storage and memory access, wherein Ray is directed towards improved data migration and preventing data corruption (para. 1). Therefore, it would be applying a known technique (providing token in cache of migrated source location; initiating a read on the destination cache responsive to retrieving the token) to a known device (device performing data migration between memories) ready for improvement to yield predictable results (device performing data migration between memories, where a token in stored to the caches of migrated source locations, and, responsive to retrieving the token from a read, another read is initiated for the destination cache in order to provide for a method for quickly establishing temporary read redirects). MPEP 2143
As per claim 16, Jayasena in view of Kanno in view of Sugimoto in view of Ray teaches claim 15 as shown above and further teaches:
16. The chip of claim 15, wherein the processor is configured to execute the program code to further cause the chip to: receive a data access request of an application for the first storage unit; and generate, in response to the data access request, the data migration request when the first storage unit meets a migration condition. [Jayasena as shown above teaches providing control information for migrating data pages (see claim 12 above) and further teaches monitoring memory accesses for updating memory usage information, such as access frequency of pages, used for page migrations between slow and faster memory (e.g. higher frequency pages moved to faster memory) (para. 27, 15, 49-40; see para. 14, 24 on memory accesses performed responsive to memory access requests from an external device having software/applications), where pages may be migrated based on conditions such as the pages’ access frequency falling below a lower threshold or above an upper threshold (para. 59, 52-53)]
As per claim 17, Jayasena in view of Kanno in view of Sugimoto in view of Ray teaches claim 16 as shown above and further teaches:
17. The chip of claim 16, wherein the first storage unit meets the migration condition when a quantity of accesses to the first storage unit reaches a value range of a migration threshold, and wherein the program code to perform data migration detection on the first storage medium comprises: detecting a data access request of the hybrid memory system, wherein the data access request indicates to access a storage unit in the hybrid memory system; and obtaining, based on the data access request, the quantity of accesses to the first storage unit. [Jayasena as shown above teaches providing control information for migrating data pages (see claims 12, 16 above) and further teaches monitoring memory accesses for updating memory usage information, such as access frequency, used for page migrations between slow and faster memory (para. 27, 15, 49-40; see para. 14, 24 on memory accesses performed responsive to memory access requests from an external device having software/applications), where pages may be migrated based on conditions such as the pages’ access frequency falling below a lower threshold or above an upper threshold (para. 59, 52-53), where, if the first storage unit is so accessed and has its memory usage information updated, the first storage unit may correspond to ‘a storage unit’ as well]
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jayasena et al. (US 20150199126 A1) in view of Kanno (US 20180247948 A1) in view of Sugimoto et al. (US 20110231594 A1) in view of Haas et al. (US 20130159609 A1) in view of Du et al. (US 20220066641 A1).
As per claim 10, Jayasena in view of Kanno in view of Sugimoto teaches claim 9 as shown above and further teaches:
10. The method of claim 9, wherein the candidate storage unit is located in a candidate storage unit queue of the second storage medium, and wherein the method further comprises: removing, after migrating the data in the first storage unit to a second storage unit, the second storage unit from the candidate storage unit queue; and adding to the candidate storage unit queue, when the candidate storage unit queue is not full of candidate storage units, a second idle storage unit that is in the second storage medium and that participates in the unified addressing. [Jayasena in view of Kanno in view of Sugimoto as shown above teaches allocating a free block from a free block pool of the destination memory as well as adding blocks to the free block pool via erasing and unmapping the blocks (see claim 1 above; Kanno: para. 98; Sugimoto: para. 44-50), where Jayasena in view of Kanno in view of Sugimoto does not recite a requirement that new blocks are added when the pool is full]
[Jayasena in view of Kanno in view of Sugimoto does not explicitly disclose a queue structure, but Haas teaches a free block queue for providing free and erased blocks for writing new and updated data to (para. 8)]
Jayasena, Kanno, Sugimoto, and Haas are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena in view of Kanno in view of Sugimoto and Haas, to modify the disclosures by Jayasena in view of Kanno in view of Sugimoto to include disclosures by Haas since they both teach data storage and memory access, wherein Haas is directed towards improved management of computerized memory (para. 17). Therefore, it would be applying a known technique (maintaining a queue of free blocks) to a known device (device maintaining a pool of free blocks for allocation) ready for improvement to yield predictable results (device maintaining a queue of free blocks for allocation in order to provide for simpler management of free blocks). MPEP 2143
Jayasena in view of Kanno in view of Sugimoto in view of Haas does not explicitly disclose, but Du discloses:
after migrating the data in the first storage unit to a second storage unit [Du teaches writing to blocks in a spare pool, where one or more blocks in the spare pool may be selected and written to, and when one or more blocks are written, the blocks are removed from the spare pool (para. 6, 21; claim 1)]
Jayasena, Kanno, Sugimoto, Haas, and Du are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena in view of Kanno in view of Sugimoto in view of Haas and Du, to modify the disclosures by Jayasena in view of Kanno in view of Sugimoto in view of Haas to include disclosures by Du since they both teach data storage and memory access, wherein Du is directed towards improved memory block management (para. 2-3). Therefore, it would be applying a known technique (writing to a block in a spare block pool and removing the block from the pool when written) to a known device (device maintaining a queue of free blocks for storing data) ready for improvement to yield predictable results (device maintaining a queue of free blocks, where a free block in the queue may be removed from the queue after being written to; doing so would provide for improved block management by ensuring that data has been successfully written to the block prior to removing the block from the queue). MPEP 2143
Claim 20 is rejected for reasons similar to claim 10 above.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Jayasena et al. (US 20150199126 A1) in view of Kanno (US 20180247948 A1) in view of Sugimoto et al. (US 20110231594 A1) in view of Zhang et al. (US 20240361942 A1).
As per claim 7, Jayasena in view of Kanno in view of Sugimoto teaches claim 5 as shown above. It does not explicitly disclose, but Zhang discloses:
7. The method of claim 5, wherein the first storage unit meets the migration condition when a first access delay of the first storage medium is less than a second access delay of the second storage medium, a first quantity of idle storage units in the first storage medium is less than or equal to a second quantity threshold, and the first storage unit is a non-idle storage unit whose quantity of accesses does not reach an access threshold, and [Jayasena as shown above teaches monitoring memory accesses for updating memory usage information including whether access frequency of a page falls below a lower threshold in migrating data between different memories (para. 27, 15, 49-40, 59, 52-53; see claim 5 above); Zhang similarly teaches determining cold data based on access frequency information, where the cold data may be migrated from high-speed memory to low-speed memory, and the first storage unit may comprise a unit storing a page of cold data (para. 35-36), and the migration may be triggered based on the current remaining available space of the high-speed memory being below a preset capacity (para. 10); while, in contrast to Jayasena’s method of comparing access frequency to a threshold, Zhang teaches determining frequency information based on access interval (para. 40-43), it would have been obvious for one of ordinary skill in the arts to have combined the references to provide for comparing a data’s access frequency against a lower access frequency threshold for determining cold data in order to provide for a method that may better account for irregular periods of bursts in activity] wherein performing the data migration detection on the first storage medium comprises: obtaining a third quantity of accesses to each storage unit in the first storage medium; and determining an idle storage unit and a non-idle storage unit in the first storage medium based on the third quantity. [Zhang teaches the cold data may be determined in response to determining the current remaining available space of the high-speed memory being below the threshold capacity (para. 48, 10), where determination of cold data may comprise evaluating of all pages at least in in the high-speed memory (para. 41-43) and migrated data determined to be cold (para. 47-48); where the locations from which cold pages were migrated may correspond to idle storage unit by the virtues of pages no longer holding data and locations continuing to store pages having non-cold data that were not migrated may correspond to non-idle storage unit]
Jayasena, Kanno, Sugimoto, and Zhang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena in view of Kanno in view of Sugimoto and Zhang, to modify the disclosures by Jayasena in view of Kanno in view of Sugimoto to include disclosures by Zhang since they both teach data storage and memory access, wherein Zhang is directed towards improved performance of heterogenous memory (para. 6). Therefore, it would be applying a known technique (responsive to remaining storage space of a faster memory falling below a capacity, determining cold data based on access characteristics and migrating cold data to a slower memory) to a known device (device performing data migration between fast and slow memories using metrics including access frequency thresholds) ready for improvement to yield predictable results (responsive to remaining storage space of a faster memory falling below a capacity, determining cold data based on access frequency of pages falling below a threshold, and migrating cold data to a slower memory; doing so would provide for improved space management of fast access memories). MPEP 2143
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jayasena et al. (US 20150199126 A1) in view of Kanno (US 20180247948 A1) in view of Sugimoto et al. (US 20110231594 A1) in view of Ray et al. (US 20170192714 A1) in view of Zhang et al. (US 20240361942 A1).
As per claim 18, Jayasena in view of Kanno in view of Sugimoto in view of Ray teaches claim 16 as shown above. It does not explicitly disclose, but Zhang teaches:
18. The chip of claim 16, wherein the first storage unit meets the migration condition when a first access delay of the first storage medium is less than a second access delay of the second storage medium, a first quantity of idle storage units in the first storage medium is less than or equal to a second quantity threshold, and the first storage unit is a non-idle storage unit whose quantity of accesses does not reach an access threshold, and [Jayasena as shown above teaches monitoring memory accesses for updating memory usage information including whether access frequency of a page falls below a lower threshold in migrating data between different memories (para. 27, 15, 49-40, 59, 52-53; see claim 16 above); Zhang similarly teaches determining cold data based on access frequency information, where the cold data may be migrated from high-speed memory to low-speed memory, and the first storage unit may comprise a unit storing a page of cold data (para. 35-36), and the migration may be triggered based on the current remaining available space of the high-speed memory being below a preset capacity (para. 10); while, in contrast to Jayasena’s method of comparing access frequency to a threshold, Zhang teaches determining frequency information based on access interval (para. 40-43), it would have been obvious for one of ordinary skill in the arts to have combined the references to provide for comparing a data’s access frequency against a lower access frequency threshold for determining cold data in order to provide for a method that may better account for irregular periods of bursts in activity] wherein the program code to perform data migration detection on the first storage medium comprises: obtaining a third quantity of accesses to each storage unit in the first storage medium; and determining an idle storage unit and a non-idle storage unit in the first storage medium based on the third quantity. [Zhang teaches the cold data may be determined in response to determining the current remaining available space of the high-speed memory being below the threshold capacity (para. 48, 10), where determination of cold data may comprise evaluating of all pages at least in in the high-speed memory (para. 41-43) and migrated data determined to be cold (para. 47-48); where the cold pages as migrated may correspond to idle storage unit by the virtues of pages no longer holding data and pages having non-cold data that were not migrated may correspond to non-idle storage unit]
Jayasena, Kanno, Sugimoto, Ray, and Zhang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jayasena in view of Kanno in view of Sugimoto in view of Ray and Zhang, to modify the disclosures by Jayasena in view of Kanno in view of Sugimoto in view of Ray to include disclosures by Zhang since they both teach data storage and memory access, wherein Zhang is directed towards improved performance of heterogenous memory (para. 6). Therefore, it would be applying a known technique (responsive to remaining storage space of a faster memory falling below a capacity, determining cold data based on access characteristics and migrating cold data to a slower memory) to a known device (device performing data migration between fast and slow memories using metrics including access frequency thresholds) ready for improvement to yield predictable results (responsive to remaining storage space of a faster memory falling below a capacity, determining cold data based on access frequency of pages falling below a threshold, and migrating cold data to a slower memory; doing so would provide for improved space management of fast access memories). MPEP 2143
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Abouelwafa et al. (US 20220244876 A1) teaches invalidating caches of migrated source memory and redirecting reads for the source memory to destination memory caches.
Conclusion
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/E.Y.K./Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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