DETAILED ACTION
Status of Claims
Claims 1 – 12 are pending.
Claims 1 and 7 are independent.
This office action is Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 4 and 10, the term “BDh command” is not defined in the Applicant’s specification nor in claims. As currently written, the metes and bounds are not clearly defined in the claim language. The Examiner takes the position that the “BDh command” refers to a command to access a register. Appropriate action is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Patent Application Publication No. 2016/0116957, hereinafter “Chen”), in view of Rollig et al. (US Patent Application Publication No. 2005/0080950, hereinafter “Rollig”).
As per claim 1, Chen teaches a power-supply management device [system management module 104, fig. 2, 0035: …the system management module (104) uses respective interfaces to manage the information handling system (102), and the management includes but is not limited to power management…. The system management module (104) has one or more signal ports for sending a control signal to the first power supply unit (116) and the second power supply unit (120) to control the operation or configuration thereof… ], comprising:
a power supply unit [power supply unit 116, fig. 3, 0039], comprising a memory [storage device 312, fig.3, 0039], the memory storing a time data [0039: …Examples of the storage device (312) include, but are not limited to, a register and cache memory. Take the register as an example, various power data, namely power data.sub.A, power data.sub.B, . . . , power data.sub.X, are stored at different addresses of the register, respectively. The various power data include the total ON duration of the first power supply unit (116), the total ON duration of the second power supply unit (120), voltage data, current data, power data, and product data… ]; and
a processor, connected to the power supply unit [0030: the system management module (104) is typically a microcontroller module operated by a monitoring system and comprises a microcontroller and a memory (not shown). The central processing unit (CPU), the system management module (104), and the like are mounted on a motherboard (not shown); 0033: The system management module (104) is electrically coupled to the first power supply unit microcontroller (204) and the second power supply unit microcontroller (224) through the communication bus (136).] and configured to:
send a control command comprising a plurality of data fields to the power supply unit [SMM sends and receives control data to power supply unit, 0035: The system management module (104) has one or more signal ports for sending a control signal to the first power supply unit (116) and the second power supply unit (120) to control the operation or configuration thereof.; 0036: The various power data include the total ON duration of the first power supply unit (116), the total ON duration of the second power supply unit (120), voltage data, current data, power data, and product data. Transfer of data between the register (312) and the system management module (104) is bidirectional. ];
access the time data [total ON duration data, 0039] and acquire a plurality of time segments of the time data by sections [0039: The various power data include the total ON duration of the first power supply unit (116), the total ON duration of the second power supply unit (120), voltage data, current data, power data, and product data. Transfer of data between the register (312) and the system management module (104) is bidirectional; 0033: The communication bus (136) operates by various protocols, such as PMBUS or SMBUS, but the present embodiment is not limited thereto. ... Data transmitted by a protocol is converted into a related command. 0047: Data transmitted by means of a protocol and its format are attributed to the prior art and thus well-known among persons skilled in the art. ] …
carry the plurality of time segments … of the time data to first of the
plurality of data fields until all the plurality of time segments are carried to the plurality of data fields; and decode the control command, and by an order starting from the time segment last carried to the plurality of data fields, assemble the plurality of time segments to obtain a power-on time of the power supply unit [0033: Data transmitted by a protocol is converted into a related command , 0039, 0047].
However, Chen does not explicitly teach “…acquire a plurality of time segments of the time data by sections from a least significant bit (LSB) of the time data according to a reading length; carry the plurality of time segments from the LSB of the time data to first of the
plurality of data fields until all the plurality of time segments are carried to the plurality of data fields…”.
Chen teaches a BMC and PSU microcontrollers are on a PMBUS/SMBUS bus [0033], and notes that protocol data and format are well-known [0047]. Rollig is cited to explicitly teach a SMBus protocol [fig. 1 – 22, 0013 -0025]. Both Chen and Rollig are directed to PMBUS/SMBUS management.
As per claim 1, Rollig further teaches …acquire a plurality of time segments of the time data by sections from a least significant bit (LSB) of the time data according to a reading length; carry the plurality of time segments from the LSB of the time data to first of the
plurality of data fields until all the plurality of time segments are carried to the plurality of data fields… [data is transferred bytewise with the MSB first1, 0007: Data are transferred bytewise, wherein every byte consists of eight bits. Each byte transferred on the bus must be followed by an acknowledge bit. Bytes are transferred with the most significant bit first].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen and Rollig, as Rollig explicitly teaches a SMBUS protocol.
As per claim 2, Rollig teaches the power-supply management device of claim 1, wherein the plurality of data fields comprise a first data field, a second data field, and a third data field, and the plurality of time segments acquired by the order starting from the LSB of the time data by the processor comprise a first time segment, a second time segment, and a third time segment, wherein the first data field carries the first time segment, the second data field carries the second time segment, and the third data field carries the third time segment, so contents of the first data field, the second data field, and the third data field are reversely arranged related to the LSB of the time data [data is transferred bytewise,0007: Data are transferred bytewise, wherein every byte consists of eight bits. Each byte transferred on the bus must be followed by an acknowledge bit. Bytes are transferred with the most significant bit first., 0022, 0028, 0079, 0084].
As per claim 3, Chen teaches the power-supply management device of claim 1, wherein fields of the control command comprise an address, and a content of the address is a memory address storing the time data of the power supply unit [SMM accesses data 0047, 0053, 0039].
As per claim 4, Chen teaches the power-supply management device of claim 1, wherein the control command is BDh command [register command, 0039] or a reserved command of Common Redundant Power Supply (CRPS) [Common Redundant Power Supply is the well know and conventional as stated by the applicant, 0014: The Common Redundant Power Supply (CRPS) is utilized as a norm of the power module of servers or storage; Chen: 0047: conventional protocols are used].
As per claim 5, Rollig teaches the power-supply management device of claim 2, wherein lengths of the first data field, the second data field, and the third data field are respectively 8 bits, a reading length is 8 bits, and the processor assembles the first time segment, the second time segment, and the third time segment to obtain the total power-on time of length 24 bits [data is transferred bytewise 0007: Data are transferred bytewise, wherein every byte consists of eight bits. Each byte transferred on the bus must be followed by an acknowledge bit. Bytes are transferred with the most significant bit first.].
As per claim 6, Rolling teaches the power-supply management device of claim 2, wherein when the processor assembles the first time segment, the second time segment, and the third time segment to obtain the total power-on time, the processor utilizes a packet error check code to examine whether the total power-on time satisfies the integrity, wherein the packet error check code is 8 bits [word protocols carry Data Byte Low then Data Byte High, figs. 8, 10, 13 – 16. Block protocols use 8-bit data bytes, figs. 17 – 22, 0007, 0013: Version 1.1 of the SMBus specification introduced a packet error checking mechanism to improve reliability and communication with busses. Packet error checking is implemented by appending a packet error code (PEC) at the end of each message transfer.].
As per claims 7- 12, it is directed to a method of steps to implement the apparatus as set forth in claims 1 - 6. Chen. In view of Rollig, teaches the claimed apparatus. Therefore, Chen, in view of Rollig teaches the method to implement the claims steps.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang; Wei-Cheng et al. (US Patent Application No. 2019/0391626 A1) “Control Method Of Redundant Power Supply Device” is cited to teach a control method that is applied to a redundant power supply device, with the redundant power supply device connected to a power demanding device and comprising a plurality of power supply units. The control method includes detecting and calculating a required electrical power value of the power demanding device, and determining an operation quantity of the power supply units according to the required electrical power value and a plurality of efficient operation data for generating a control command, and selectively controlling the redundant power supply device according to the control command. Additionally, wherein the plurality of efficient operation data indicates a relationship between supplied power of the redundant power supply device and the operation quantity of the power supply units, and the relationship is associated with a power supply efficiency of the redundant power supply device.
Kao; Chin-Jun. (US Patent Application Publication No. 2018/0356469) “Electronic System And Method For Recognizing Status Of Power-Supply Device” is cited to teach an electronic system and a method for recognizing status of a power-supply device. The electronic system includes a power-supply device and an electronic device. The power-supply device generates a working power and stores an accumulated operation time length and a suggested operation time length of the power-supply device. The electronic device is coupled to the power-supply device and receives the working power to perform a booting operation. The electronic device reads the accumulated operation time length and the suggested operation time length from the power-supply device and compares the accumulated operation time length and the suggested operation time length. If the accumulated operation time length is greater than or equal to the suggested operation time length, the electronic device generates a warning message to indicate that the power-supply device has reached a lifetime.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERRELL S JOHNSON whose telephone number is (571)270-3485. The examiner can normally be reached 10AM-7PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TERRELL S JOHNSON/Primary Examiner, Art Unit 2176
1 Adapting the order of the bytewise transfer is a design choice, as sending the data as segments instead of the entire data field/segment reduces transmission time.
